Application of swarm intelligence techniques to the design of analog circuits: evaluation and comparison

A Sallem, B Benhala, M Kotti, M Fakhfakh… - … Integrated Circuits and …, 2013 - Springer
Swarm intelligence (SI) techniques are more and more used by analog designers in order to
optimally size their circuits/systems' performances. A particular interest is accorded to the …

[PDF][PDF] Application of the ACO technique to the optimization of analog circuit performances

B Benhala, A Ahaitouf, M Kotti, M Fakhfakh… - Optimization …, 2011 - researchgate.net
This chapter presents an adaptation of the Ant Colony Optimization technique to the optimal
sizing of analog circuits. Details of the proposed algorithm are given in the following …

Analogue circuit optimization through a hybrid approach

M Fakhfakh, A Sallem, M Boughariou… - Intelligent computational …, 2011 - Springer
Optimal analogue circuit sizing is investigated in this chapter. It is shown that hybridization of
a global optimization approach with a local one leads to better results in optimization of such …

Application of the PSO technique to the Optimization of CMOS Operational Transconductance Amplifiers

S Bennour, A Sallem, M Kotti, E Gaddour… - … on Design & …, 2010 - ieeexplore.ieee.org
In this paper, we investigate the Optimizing Operational Transconductance Amplifiers
through the constrained Particle Swarm Optimization (PSO). We optimize the folded cascode …

On the design of active inductors with current-controlled voltage sources

M Fakhfakh, M Pierzchała, B Rodanski - Analog Integrated Circuits and …, 2012 - Springer
This paper presents a novel method of designing active inductors using current-controlled
voltage sources (CCVSs). The basic idea consists of designing an equivalent inductor, using …

Synthesis of active inductors using SFG stamps

M Fakhfakh, M Pierzchała - Microelectronics Journal, 2013 - Elsevier
This paper proposes a new approach for the systematic synthesis of active inductors via
signal-flow graphs (SFGs). The basic idea consists of proposing and using SFG stamps of …

Design of sample-and-hold circuit for a reconfigurable ADC

Y Xiang, F Xiangning, Z Hao - 2012 International Conference …, 2012 - ieeexplore.ieee.org
In this paper, a sample-and-hold circuit for a reconfigurable ADC is presented. This design is
based on TSMC 0.18 μm process. Flip-around architecture is employed to implement overall …

Design of discret time feed-forward cascaded ΔΣ modulator for wireless communication systems

H Daoud, D Laouej, SB Salem… - 2016 11th International …, 2016 - ieeexplore.ieee.org
This paper presents the design of discret time (DT) feed-forward (FF) 2-1 cascaded Delta-
Sigma (ΔΣ) modulator used in wireless communication systems. This topology can provide …

Artificial bee colony technique for optimal design of folded cascode OTA

B Benhala - … Conference on Applied Mathematics & Computer …, 2018 - ieeexplore.ieee.org
This paper presents an application of a Swarm Intelligence (SI) algorithm for automatic
sizing of analog circuits. For this purpose, a CMOS folded cascode Operational …

An improved design of VCCS-based active inductors

M Fakhfakh, M Pierzchala… - … Conference on Synthesis …, 2012 - ieeexplore.ieee.org
In this paper we present an enhanced design of active inductors. The idea mainly consists of
improving classical voltage controlled current source-based simulated inductors' …