Performance loss due to long-latency memory accesses can be reduced by servicing
multiple memory accesses concurrently. The notion of generating and servicing long-latency …

Irregular workloads are typically bottlenecked by the memory system. These workloads often
use sparse data representations, eg, compressed sparse row/column (CSR/CSC), to …

Runahead execution pre-executes the application's own code to generate new cache
misses. This pre-execution results in prefetch requests that are overwhelmingly accurate …

This paper presents a novel approach to utilize the CPU resource to facilitate the execution
of GPGPU programs on fused CPU-GPU architectures. In our model of fused architectures …

Data prefetching is an effective data access latency hiding technique to mask the CPU stall
caused by cache misses and to bridge the performance gap between processor and …

Today's computers employ significant heterogeneity to meet performance targets at
manageable power. In adopting increased compute specialization, however, the relative …

Chip multiprocessors with multiple simpler cores are gaining popularity because they have
the potential to drive future performance gains without exacerbating the problems of power …

This paper describes a new technique in the Network Weather Service for producing multi-
variate forecasts. The new technique uses the NWS's univariate forecasters and emprically …

Under current worst-case design practices, manufacturers specify conservative values for
processor frequencies in order to guarantee correctness. To recover some of the lost …

Today's high-performance processors face main-memory latencies on the order of hundreds
of processor clock cycles. As a result, even the most aggressive processors spend a …