Low Latency and High Throughput Pipelined Online Adder for Streaming Inner Product

T Arifeen, S Gorgin, MH Gholamrezaei… - Journal of Signal …, 2023 - Springer
Low latency computation is vital to meet real-time constraints in many Convolutional Neural
Networks (CNN) based applications such as autonomous vehicles. To enable low latency …

Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits

G Jaberipur, B Parhami - IET computers & digital techniques, 2012 - IET
Most common uses of negatively weighted bits (negabits), normally assuming arithmetic
value− 1 (0) for logical 1 (0) state, are as the most significant bit of 2's-complement numbers …

Reviewing high-radix signed-digit adders

P Kornerup - IEEE Transactions on Computers, 2014 - ieeexplore.ieee.org
Higher radix values of the form β= 2 r have been employed traditionally for recoding of
multipliers, and for determining quotientand root-digits in iterative division and square root …

A family of high radix signed digit adders

S Gorgin, G Jaberipur - 2011 IEEE 20th Symposium on …, 2011 - ieeexplore.ieee.org
Signed digit (SD) number systems allow for high performance carry-free adders. Maximally
redundant SD (MRSD) alternatives provide maximal encoding efficiency among Radix-2 h …

QCA-Based Adder for Redundant Binary Signed Digit Numbers

M Mohtashami, M Khalily-Dermany - Arabian Journal for Science and …, 2022 - Springer
Redundant binary signed digit (RBSD) system is used implicitly or explicitly to provide a fast
and propagation-free addition in many digital systems. Furthermore, supporting negative …

Posibits, negabits, and their mixed use in efficient realization of arithmetic algorithms

G Jaberipur, B Parhami - 2010 15th CSI International …, 2010 - ieeexplore.ieee.org
Positively weighted and negatively weighted bits (posibits, negabits) have been used in the
interpretation of 2's-complement, negative-radix, and binary signed-digit number …

[PDF][PDF] Hybrid signed digit arithmetic in efficient computing: A comparative approach to performance assay

V Awasthi, K Raj - Novel Perspectives Eng. Res, 2021 - researchgate.net
In redundant representations, addition can be performed in a constant time independent of
the word length of the operands. In practically all VLSI designs, the adder serves as a …

Підвищення ефективності багатомісних обчислень на ПЛІС

ІМ Вербовський - 2024 - ela.kpi.ua
Анотація Дана робота присвячена дослідженню методів підвищення ефективності
багатомісних обчислень на ПЛІС. Основна увага приділяється розробці нових підходів …

Low latency prefix accumulation driven compound MAC unit for efficient FIR filter implementation

GR Hemantha, S Varadarajan, MN Giriprasad - 2020 - nopr.niscpr.res.in
This article presents hierarchical single compound adder-based MAC with assertion based
error correction for speculation variations in the prefix addition for FIR filter design. The VLSI …

Extended redundant-digit instruction set for energy-efficient processors

S Amanollahi, G Jaberipur - ACM Transactions on Embedded …, 2018 - dl.acm.org
The impact of extending the instruction set architecture (ISA) of a conventional binary
processor by a set of redundant-digit arithmetic instructions is studied. Selected binary …