[HTML][HTML] Time-to-digital conversion techniques: A survey of recent developments
J Szyduczyński, D Kościelnik, M Miśkowicz - Measurement, 2023 - Elsevier
Time-to-digital converters (TDCs) are key components of time-mode circuits and enablers for
digital processing of analog signals encoded in time. Since design of time-mode circuits …
digital processing of analog signals encoded in time. Since design of time-mode circuits …
Recent developments and design challenges of high-performance ring oscillator CMOS time-to-digital converters
Time-to-digital converters (TDCs) are increasingly used as building blocks in biomedical
imaging, digital communication, and measurement instrumentation systems. When …
imaging, digital communication, and measurement instrumentation systems. When …
[图书][B] High-frequency integrated circuits
S Voinigescu - 2013 - books.google.com
A transistor-level, design-intensive overview of high speed and high frequency monolithic
integrated circuits for wireless and broadband systems from 2 GHz to 200 GHz, this …
integrated circuits for wireless and broadband systems from 2 GHz to 200 GHz, this …
A 56.4-to-63.4 GHz multi-rate all-digital fractional-N PLL for FMCW radar applications in 65 nm CMOS
W Wu, RB Staszewski, JR Long - IEEE Journal of solid-state …, 2014 - ieeexplore.ieee.org
A mm-wave digital transmitter based on a 60 GHz all-digital phase-locked loop (ADPLL) with
wideband frequency modulation (FM) for FMCW radar applications is proposed. The …
wideband frequency modulation (FM) for FMCW radar applications is proposed. The …
A Bluetooth low-energy transceiver with 3.7-mW all-digital transmitter, 2.75-mW high-IF discrete-time receiver, and TX/RX switchable on-chip matching network
FW Kuo, SB Ferreira, HNR Chen… - IEEE Journal of Solid …, 2017 - ieeexplore.ieee.org
We present an ultra-low-power Bluetooth low-energy (BLE) transceiver (TRX) for the Internet
of Things (IoT) optimized for digital 28-nm CMOS. A transmitter (TX) employs an all-digital …
of Things (IoT) optimized for digital 28-nm CMOS. A transmitter (TX) employs an all-digital …
A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB
AT Narayanan, M Katsuragi, K Kimura… - IEEE Journal of Solid …, 2016 - ieeexplore.ieee.org
A fractional-N sub-sampling PLL architecture based on pipelined phase-interpolator and
Digital-to-Time-Converter (DTC) is presented in this paper. The combination of pipelined …
Digital-to-Time-Converter (DTC) is presented in this paper. The combination of pipelined …
A fully integrated Bluetooth low-energy transmitter in 28 nm CMOS with 36% system efficiency at 3 dBm
We propose a new transmitter architecture for ultra-low power radios in which the most
energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS …
energy-hungry RF circuits operate at a supply just above a threshold voltage of CMOS …
A 3.6 mW, 90 nm CMOS gated-Vernier time-to-digital converter with an equivalent resolution of 3.2 ps
Two gated ring oscillators (GROs) act as the delay lines in an improved Vernier time-to-
digital converter (TDC), where the already small quantization noise of the standard Vernier …
digital converter (TDC), where the already small quantization noise of the standard Vernier …
Time Moore: Exploiting Moore's Law from the perspective of time
L Xiu - IEEE Solid-State Circuits Magazine, 2019 - ieeexplore.ieee.org
Moore's law has served as a goal for the semiconductor industry for more than 50 years.
After decades of relentlessly racing forward, convincing new evidence now shows that the …
After decades of relentlessly racing forward, convincing new evidence now shows that the …
A compact, low-power and low-jitter dual-loop injection locked PLL using all-digital PVT calibration
This paper presents a low-jitter, low-power and a small-area injection-locked all-digital PLL
(IL-ADPLL). It consists of a dual-loop and a dual-VCO architecture in which one VCO …
(IL-ADPLL). It consists of a dual-loop and a dual-VCO architecture in which one VCO …