Branch predictor (BP) is an essential component in modern processors since high BP
accuracy can improve performance and reduce energy by decreasing the number of …

As technology scales, interconnects have become a major performance bottleneck and a
major source of power consumption for microprocessors. Increasing interconnect costs …

In response to increasing (relative) wire delay, architects have proposed various
technologies to manage the impact of slow wires on large uniprocessor L2 caches. Block …

It is now widely admitted that in order to provide state-of-the-art accuracy, a conditional
branch predictor must combine several predictions. Recent research has shown that an …

The TAGE predictor is often considered as state-of-the-art in conditional branch predictors
proposed by academy. In this paper, we first present directions to reduce the hardware …

Microarchitectural prediction based on neural learning has received increasing attention in
recent years. However, neural prediction remains impractical because its superior accuracy …

Data prefetching effectively reduces the negative effects of long load latencies on the
performance of modern processors. Hardware prefetchers employ hardware structures to …

3D integration technology greatly increases transistor density while providing faster on-chip
communication. 3D implementations of processors can simultaneously provide both latency …

Outline In this study, we explore the performance limits of these TAGE-SC-L predictors for
respectively 8Kbytes and 64Kbytes of storage budget. For a 8KB storage budget, our …

In this paper, we introduce and analyze the Optimized GEometric History Length (O-GEHL)
branch Predictor that efficiently exploits very long global histories in the 100-200 bits range …