Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization
In linear IC's fabricated in a low-voltage CMOS technology, the reduction of the dynamic
range due to the dc offset and low frequency noise of the amplifiers becomes increasingly …
range due to the dc offset and low frequency noise of the amplifiers becomes increasingly …
[图书][B] Analog design for CMOS VLSI systems
F Maloberti - 2006 - books.google.com
Analog Design for CMOS VLSI Systems is a comprehensive text that offers a detailed study
of the background principles and the analog design techniques for CMOS-VLSI …
of the background principles and the analog design techniques for CMOS-VLSI …
Design Trends and Perspectives of Digital Low Dropout Voltage Regulators for Low Voltage Mobile Applications: A Review
Low-dropout (LDO) voltage regulator has fascinated industry professionals and academia
for the past few decades, and this trend is expected to continue in the coming years. The …
for the past few decades, and this trend is expected to continue in the coming years. The …
Analyses of static and dynamic random offset voltages in dynamic comparators
J He, S Zhan, D Chen, RL Geiger - IEEE Transactions on …, 2009 - ieeexplore.ieee.org
When mismatches are present in a dynamic comparator, due to internal positive feedback
and transient response, it is always challenging to analytically predict the input-referred …
and transient response, it is always challenging to analytically predict the input-referred …
Split capacitor DAC mismatch calibration in successive approximation ADC
Y Chen, X Zhu, H Tamura, M Kibune… - IEICE transactions on …, 2010 - search.ieice.org
Charge redistribution based successive approximation (SA) analog-to-digital converter
(ADC) has the advantage of power efficiency. Split capacitor digital-to-analog converter …
(ADC) has the advantage of power efficiency. Split capacitor digital-to-analog converter …
A 12-bit 10 MS/s SAR ADC with high linearity and energy-efficient switching
S Liu, Y Shen, Z Zhu - … Transactions on Circuits and Systems I …, 2016 - ieeexplore.ieee.org
A 12-bit 10 MS/s SAR ADC with enhanced linearity and energy efficiency is presented in this
paper. A novel switching scheme (COSS) is proposed to reduce the power consumption and …
paper. A novel switching scheme (COSS) is proposed to reduce the power consumption and …
A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-/spl mu/m digital CMOS
C Sandner, M Clara, A Santner… - IEEE Journal of Solid …, 2005 - ieeexplore.ieee.org
We present a 6-bit 1.2-GS/s flash-ADC with wide analog bandwidth and low power, realized
in a standard digital 0.13/spl mu/m CMOS copper technology. Employing capacitive …
in a standard digital 0.13/spl mu/m CMOS copper technology. Employing capacitive …
An analysis of latch comparator offset due to load capacitor mismatch
A Nikoozadeh, B Murmann - … on Circuits and Systems II: Express …, 2006 - ieeexplore.ieee.org
This brief analyzes the effect of load capacitor mismatch on the offset of a regenerative latch
comparator. Two analytical models are presented and compared with HSpice simulations …
comparator. Two analytical models are presented and compared with HSpice simulations …
[图书][B] Design for reliability of low-voltage, switched-capacitor circuits
AM Abo - 1999 - search.proquest.com
Analog, switched-capacitor circuits play a critical role in mixed-signal, analog-to-digital
interfaces. They implement a large class of functions, such as sampling, filtering, and …
interfaces. They implement a large class of functions, such as sampling, filtering, and …
A low-power high-speed comparator for precise applications
A Khorami, M Sharifkhani - IEEE Transactions on Very Large …, 2018 - ieeexplore.ieee.org
A low-power comparator is presented. pMOS transistors are used at the input of the
preamplifier of the comparator as well as the latch stage. Both stages are controlled by a …
preamplifier of the comparator as well as the latch stage. Both stages are controlled by a …