A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a 62.1-dBc Fractional Spur
This article presents a 7-GHz fractional-N digital phase-locked loop (DPLL) without any
digital pre-distortion (DPD) on the integral nonlinearity (INL) of the digital-to-time converter …
digital pre-distortion (DPD) on the integral nonlinearity (INL) of the digital-to-time converter …
A Calibration-Free Fractional-N Analog PLL With Negligible DSM Quantization Noise
An analog fractional-N phase-locked loop (PLL) is presented, which largely eliminates
quantization noise by overclocking the delta–sigma modulator (DSM). The overclocking …
quantization noise by overclocking the delta–sigma modulator (DSM). The overclocking …
A Low-Jitter Fractional- Digital PLL Adopting a Reverse-Concavity Variable-Slope DTC
This article presents a fractional-digital-to-time converter (DTC)-based digital phase-locked
loop (PLL), achieving simultaneously low phase noise and low spurious tones. The PLL …
loop (PLL), achieving simultaneously low phase noise and low spurious tones. The PLL …
A Low Phase Noise Frequency Synthesizer with a Fourth-Order RLC Loop Filter
X Zhang, Q Du, C Liu, H Zhang, Y Ma, Y Li, J Li - Electronics, 2023 - mdpi.com
The current work employs the HMC830 phase-locked loop chip to design a frequency
synthesizer operating in the L-band. The frequency synthesizer can provide a local …
synthesizer operating in the L-band. The frequency synthesizer can provide a local …
A 28.8-to-43.2 GHz 79.8 fs Jitter and 78.5 dBc Reference Spur PLL Exploiting Complementary Mixing Phase Detector With Mismatch Calibration
Millimeter-wave (mmW) phase-locked loops (PLLs) prefer large loop bandwidth for
suppressing more voltage-controlled oscillator (VCO) phase noise, which, in turn, degrades …
suppressing more voltage-controlled oscillator (VCO) phase noise, which, in turn, degrades …
A 5–18-GHz Reconfigurable Quadrature Receiver With Enhanced I–Q Isolation and 100–500-MHz Baseband Bandwidth
J Bi, H Xu, T Zou, Y Zeng, Y Tian, W He… - IEEE Journal of Solid …, 2024 - ieeexplore.ieee.org
A wideband reconfigurable quadrature receiver with the range of 5–18-GHz frequency
coverage and 100–500-MHz analog baseband bandwidth is proposed in this article. The …
coverage and 100–500-MHz analog baseband bandwidth is proposed in this article. The …
A Harmonic-Mixer-Based Fractional-N PLL Employing Voltage-Domain Feed-Forward Noise Cancellation
H Zhang, M Osada, Y Zhu… - IEEE Journal of Solid-State …, 2024 - ieeexplore.ieee.org
A harmonic-mixer (HM)-based fractional-N phase-locked loop (PLL) employing voltage-
domain feed-forward noise cancellation (FFNC) is presented in this article. By adding the …
domain feed-forward noise cancellation (FFNC) is presented in this article. By adding the …
A Sub-50-fs Jitter Fractional- CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector With Cascadable DTC Nonlinearity …
A 24–28-GHz sub-50-fsrms jitter fractional-charge pump phase-locked loop (CPPLL) is
presented in this work. A dual-digital-to-time converter (DTC)-assisted time-amplifying phase …
presented in this work. A dual-digital-to-time converter (DTC)-assisted time-amplifying phase …
A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering
A phase-locked loop (PLL) employing a split-feedback divider and nested-PLL-based phase-
domain low-pass filter (PDLPF) within the harmonic-mixer (HM)-based dual-feedback …
domain low-pass filter (PDLPF) within the harmonic-mixer (HM)-based dual-feedback …
An 88.5 fs Integrated Jitter and 76.2 dBc Reference Spur mmW PLL Utilizing a Ripple Compensation Phase/Frequency Detector
Millimeter-wave (mmW) phase-locked loops (PLLs) typically favor a wide loop bandwidth for
stronger suppression of the out-of-band phase noise from a voltage-controlled oscillator …
stronger suppression of the out-of-band phase noise from a voltage-controlled oscillator …