A 56-Gb/s PAM4 receiver with low-overhead techniques for threshold and edge-based DFE FIR-and IIR-tap adaptation in 65-nm CMOS
A Roshan-Zamir, T Iwai, YH Fan… - IEEE Journal of Solid …, 2018 - ieeexplore.ieee.org
This paper presents a four-level pulse amplitude modulation (PAM4) quarter-rate receiver
that efficiently compensates for moderate channel loss in a robust manner through …
that efficiently compensates for moderate channel loss in a robust manner through …
A 112 Gb/s PAM-4 56 Gb/s NRZ reconfigurable transmitter with three-tap FFE in 10-nm FinFET
J Kim, A Balankutty, RK Dokania… - IEEE Journal of Solid …, 2018 - ieeexplore.ieee.org
This paper presents a reconfigurable 56 GS/s transmitter (TX) that operates up to 112 Gb/s
with four-level pulse-amplitude modulation (PAM-4) and at 56 Gb/s with non-return-to-zero …
with four-level pulse-amplitude modulation (PAM-4) and at 56 Gb/s with non-return-to-zero …
A 64-Gb/s 4-PAM transceiver utilizing an adaptive threshold ADC in 16-nm FinFET
L Wang, Y Fu, MA LaCroix, E Chong… - IEEE Journal of Solid …, 2018 - ieeexplore.ieee.org
A 64-Gb/s 4-pulse-amplitude modulation (PAM) transceiver fabricated with a 16-nm fin field
effect transistor (FinFET) technology is presented with a power consumption that scales with …
effect transistor (FinFET) technology is presented with a power consumption that scales with …
A 64 Gb/s low-power transceiver for short-reach PAM-4 electrical links in 28-nm FDSOI CMOS
E Depaoli, H Zhang, M Mazzini… - IEEE Journal of Solid …, 2018 - ieeexplore.ieee.org
A four-level pulse-amplitude modulation (PAM-4) transceiver operating up to 64 Gb/s in 28-
nm CMOS fully depleted silicon-on-insulator (FDSOI) for short-reach electrical links is …
nm CMOS fully depleted silicon-on-insulator (FDSOI) for short-reach electrical links is …
A 1.17-pJ/b, 25-Gb/s/pin ground-referenced single-ended serial link for off-and on-package communication using a process-and temperature-adaptive voltage …
JW Poulton, JM Wilson, WJ Turner… - IEEE Journal of Solid …, 2018 - ieeexplore.ieee.org
This paper describes a short-reach serial link to connect chips mounted on the same
package or on neighboring packages on a printed circuit board (PCB). The link employs an …
package or on neighboring packages on a printed circuit board (PCB). The link employs an …
Review of CMOS integrated circuit technologies for high-speed photo-detection
The bandwidth requirement of wireline communications has increased exponentially
because of the ever-increasing demand for data centers and high-performance computing …
because of the ever-increasing demand for data centers and high-performance computing …
6.2 A 60Gb/s PAM-4 ADC-DSP transceiver in 7nm CMOS with SNR-based adaptive power scaling achieving 6.9 pJ/b at 32dB loss
MA LaCroix, H Wong, YH Liu, H Ho… - … Solid-State Circuits …, 2019 - ieeexplore.ieee.org
With the introduction of PAM-4 signaling at 56Gb/s and the decreased benefits of CMOS
scaling for high-speed mixed-signal designs, SerDes designers and system architects are …
scaling for high-speed mixed-signal designs, SerDes designers and system architects are …
30-Gb/s 1.11-pJ/bit single-ended PAM-3 transceiver for high-speed memory links
A 30-Gb/s three-level pulse amplitude modulation (PAM-3) transceiver is designed with a
one-tap tri-level decision feedback equalizer (DFE) to realize a high-speed dynamic random …
one-tap tri-level decision feedback equalizer (DFE) to realize a high-speed dynamic random …
A 56-Gb/s 50-mW NRZ Receiver in 28-nm CMOS
A wireline receiver consisting of a linear equalizer, a decision-feedback equalizer (DFE), a
clock and data recovery (CDR) circuit, and a demultiplexer (DMUX) employs new circuit and …
clock and data recovery (CDR) circuit, and a demultiplexer (DMUX) employs new circuit and …
A 60-Gb/s PAM4 wireline receiver with 2-tap direct decision feedback equalization employing track-and-regenerate slicers in 28-nm CMOS
KC Chen, WWT Kuo, A Emami - IEEE Journal of Solid-State …, 2020 - ieeexplore.ieee.org
This article describes a 4-level pulse amplitude modulation (PAM4) receiver incorporating
continuous time linear equalizers (CTLEs) and a 2-tap direct decision feedback equalizer …
continuous time linear equalizers (CTLEs) and a 2-tap direct decision feedback equalizer …