This paper presents an innovative approach for predicting timing errors tailored to near-/sub-
threshold operations, addressing the energy-efficient requirements of digital circuits in …

Specialized architecture combined with near-and subthreshold voltage circuits emerges as
a promising candidate to improve the energy efficiency in performing complex computing …

This article presents internal error detection, correction, and latching (iEDCL), a designer-
friendly, fully functional error detection and correction (EDAC) approach tailored for energy …

Operating at lower supply voltages to meet ever-increasing demands for power-efficiency
unfortunately aggravates process, voltage, and temperature (PVT) variability. Resilient …

The digital designs operating in sub/near-threshold region are susceptible to timing errors
due to the extreme impact of process, voltage, and temperature (PVT) variations. This paper …

The error-detecting latch (EDL), which consists of a latch and a transition detector (TD), is
the key circuit to the success of timing-error resilient system design. In order to realize a truly …

Resilient circuits are becoming a popular alternative to cope with process, voltage, and
temperature variability under ultra-deep-submicron technology. Timing resilient …

As the VLSI design moves into ultra-deep-submicron technologies, timing margins added
due to variabilities in the manufacturing process, operation temperature and supply voltage …

The increasing impact of variability on near-threshold nanometer circuits calls for a tighter
online monitoring and control of the available timing margins. Error-detection sequentials …

Advances in the manufacturing processes of microelectronics devices led to an increase
miniaturization of the Field Eect Transistors (FETs), reaching nanometer scale nowadays …