An embodiment of the present invention provides a phase locked loop that operates on
clock signals derived from an RF clock signal generated by the phase locked loop. A …

H03M1/0634—Continuously compensating for, or preventing, undesired influence of
physical parameters characterised by the use of methods or means not specific to a …

BACKGROUND An all-digital phase locked loop (ADPLL) is a circuit that locks the phase of
a local oscillator clock signal, output from the ADPLL, to the phase of a frequency reference …

The present invention is generally directed to a digital clock system that may be used to
generate a clock for a circuit system. In particular, the present invention is directed to a clock …

(21) Appl. No.: 12/411,482 Transmission of information between user equipment (UE) and
base stations in a wireless network occurs using a stream (22) Filed: Mar. 26, 2009 of …

Phase error of a time-to-digital converter (TDC) within an all-digital phase-locked loop
(ADPLL) is compensated by predicting possible phase error, which are predicted accord ing …

A digitally controlled mechanism for the minimization of the self-interference caused by an
amplitude modulated signal generated within a polar transmitter to the oscillator circuit …

It is therefore an aim of the invention to provide an improved gain normalization of a time-to-
digital converter. 0009. In accordance with a first aspect of the invention, there is provided a …

For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop
(ADPLL) with digital compo nents and digital operations is used. The ADPLL may also be …

Abstract A digital Phase Locked Loop (PLL) in a wireless communication system is provided.
The PLL includes a Digitally Controlled Oscillator (DCO), a divider, a Phase Frequency …