Survey on hardware implementation of random number generators on FPGA: Theory and experimental analyses
Random number generation refers to many applications such as simulation, numerical
analysis, cryptography etc. Field Programmable Gate Array (FPGA) are reconfigurable …
analysis, cryptography etc. Field Programmable Gate Array (FPGA) are reconfigurable …
Radix-2w Arithmetic for Scalar Multiplication in Elliptic Curve Cryptography
AK Oudjida, A Liacha - … Transactions on Circuits and Systems I …, 2021 - ieeexplore.ieee.org
Elliptic curve scalar multiplication k. P, where k is a nonnegative constant and P is a point on
the elliptic curve, requires two distinct operations: addition (ADD) and doubling (DBL). To …
the elliptic curve, requires two distinct operations: addition (ADD) and doubling (DBL). To …
Power and area efficient FIR filter using Radix- 2r multiplier for de-noise the electrooculography (EOG) signal
GK Kumar, NR Chinnapurapu, K Srinivas - Scientific Reports, 2024 - nature.com
This article introduces a novel FIR filter using a Radix-2r multiplier combined with 4: 2 and 3:
2 compressors for denoising Electrooculography (EOG) signals. This approach replaces …
2 compressors for denoising Electrooculography (EOG) signals. This approach replaces …
Multiple constant multiplication algorithm for high-speed and low-power design
In this brief, Radix-2 r arithmetic is applied to the multiple constant multiplication (MCM)
problem. Given a number M of nonnegative constants with a bit length N, we determine the …
problem. Given a number M of nonnegative constants with a bit length N, we determine the …
Design of high‐speed, low‐power, and area‐efficient FIR filters
In a recent work, we have introduced a new multiple constant multiplication (MCM)
algorithm, denoted as RADIX‐2r. The latter exhibits the best results in speed and power …
algorithm, denoted as RADIX‐2r. The latter exhibits the best results in speed and power …
Design and FPGA implementation of lattice wave fractional order digital differentiator
This paper deals with the design and FPGA implementation of a fractional order digital
differentiator. It is realized using computationally efficient lattice wave digital filter (LWDF) …
differentiator. It is realized using computationally efficient lattice wave digital filter (LWDF) …
Radix-2r Arithmetic for Multiplication by a Constant: Further Results and Improvements
AK Oudjida, N Chaillet… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
In a previous brief, we proposed a new sublinear-runtime recoding heuristic for the
multiplication by a constant, accompanied by its upper bound complexity. In this brief, further …
multiplication by a constant, accompanied by its upper bound complexity. In this brief, further …
Power and Delay Efficient Haar Wavelet Transform for Image Processing Application
This paper presents a one-level decomposition Haar Discrete Wavelet Transform (DWT)
architecture using a 4: 2 compressor and carry propagate adder. In Haar DWT architecture …
architecture using a 4: 2 compressor and carry propagate adder. In Haar DWT architecture …
Area efficient 2D FIR filter architecture for image processing applications
S Cheemalakonda, S Chagarlamudi… - … on Devices, Circuits …, 2022 - ieeexplore.ieee.org
The 2D-finite impulse response filters are efficient and are of low complexity and they are
often used for image restoration, image enhancement and denoising applications. The 2D …
often used for image restoration, image enhancement and denoising applications. The 2D …
FPGA Implementation of Lattice-Wave Half-Order Digital Integrator using Radix- Digit Recoding
This paper presents the FPGA implementation of half-order digital integrator configured in
lattice wave digital structure. The optimal lattice wave coefficients for 3 rd and 5 th structure …
lattice wave digital structure. The optimal lattice wave coefficients for 3 rd and 5 th structure …