With the growing complexity of railway control systems, it is required to preform runtime
safety checks of system executions that go beyond conventional runtime monitoring of pre …

The security architecture of modern systems-on-a-chip (SoC) is complex and critical to be
done right and quickly. SoC security architects feel an acute need for new tool-supported …

A problem with most runtime verification techniques is that the monitoring specification
formalisms are often complex. In this paper, we propose an extension of live sequence …

Runtime verification is a lightweight formal method that checks whether an execution of a
system satisfies a given property. A challenge in building a runtime verification system is to …

Due to the increasing complexity of modern digital designs using NoC (network-on-chip)
communication, post-silicon validation has become and arduous task that consumes much …

Getrieben durch technische Innovationen gewinnt die Kommunikation zwischen
eingebetteten Systemen immer mehr an Bedeutung. So kommunizieren heutzutage nicht …

Due to the increasing complexity of modern digital designs using NoC (network-on-chip)
communication, post-silicon validation has become an arduous task that consumes much of …

抄録 コンポーネントを利用したソフトウェアを設計する際, シーケンス図が幅広く利用されている.
しかし, 従来シーケンス図の正しさを自動的に検証することは困難であった. 我々はシーケンス図を …

JAIST Repository Page 1 Japan Advanced Institute of Science and Technology JAIST
Repository https://dspace.jaist.ac.jp/ Title プロセス代数に基づく非決定的なシナリオ合成による …