Apparatuses and methods for generating multiple row hammer address refresh sequences.
An example apparatus may include an address scrambler and a refresh control circuit. The …

Embodiments of the disclosure are drawn to apparatuses and methods for scheduling
targeted refreshes in a memory device. Memory cells in a memory device may be volatile …

Apparatuses and methods for distributing row hammer refresh events across a memory
device is disclosed. In one embodiment, the present disclosure is directed to an apparatus …

Apparatuses and methods for triggering row hammer address sampling are described. An
example apparatus includes an oscillator circuit configured to provide a clock signal, and a …

The address of victim rows may be determined based on rows that are accessed in a
memory. The victim addresses may be stored and associated with a count for every time a …

Int. CI. GIIC 11/406(2006.01) GIIC 11/408(2006.01)(52) US Cl. CPC GIIC 11/40618
(2013.01); GIIC 11/408 (2013.01); GIIC 11/40615 (2013.01); G11C 11/40622 (2013.01)(58) …

Embodiments of the disclosure are drawn to apparatuses and methods for scheduling
targeted refreshes in a memory device. Memory cells in a memory device may be volatile …

Embodiments of the disclosure are drawn to apparatuses and methods for staggering the
timing of targeted refresh operations. Memory dies may need to periodically perform refresh …

Embodiments of the disclosure are drawn to apparatuses and methods for distributed timing
of targeted refresh opera tions. Information stored in volatile memory cells may decay unless …

An apparatus may include multiple address registers each storing an address signal and
multiple counter circuits each storing a count value corresponding to an associated one of …