Abstract Systems and methods described herein are directed to solutions for NoC
interconnects that provide congestion avoidance and end-to-end uniform and weighted-fair …

Example implementations described herein are directed to a system on chip (SoC) that can
include a plurality of blocks of substantially non-uniform shapes and dimensions, a plurality …

Abstract Systems and methods described herein are directed to streaming bridge design
implementations that help interconnect and transfer transaction packets between multiple …

Abstract Systems and methods for automatically building a deadlock free inter-
communication network in a multi-core system are described. The example embodiments …

Abstract Systems and methods involving construction of a system interconnect in which
different channels have different widths in numbers of bits. Example processes to construct …

Aspects of the present disclosure relate to a method and system for hybrid and/or distributed
implementation of generation and/or execution of power profile management instructions …

Addition, search, and performance of other allied activities relating to keys are performed in
a hardware hash table. Further, high performance and efficient design may be pro vided for …

Example implementations described herein are directed to a configurable building block,
such as a router, for implementation of a Network on Chip (NoC). The router is …

8,136,071 8,281.297 8,312.402 8.448, 102 8.492. 886 8,541,819 8,543,964 8,601.423
8,635,577 8,667,439 8,717,875 2002fOO71392 2002fOO73380 2002fO095430 …

US9158882B2 - Automatic pipelining of NoC channels to meet timing and/or performance -
Google Patents US9158882B2 - Automatic pipelining of NoC channels to meet timing and/or …