A real-time Naive Bayes classifier accelerator on FPGA
Z Xue, J Wei, W Guo - IEEE Access, 2020 - ieeexplore.ieee.org
In this paper, we propose a real-time hardware naive Bayes classifier (NBC) which is
implemented on field programmable gate array (FPGA). We first use logarithm …
implemented on field programmable gate array (FPGA). We first use logarithm …
An error-efficient Gaussian filter for image processing by using the expanded operand decomposition logarithm multiplication
Digital signal processing and image processing applications require the noise free and
efficient arithmetic operations. To overcome the noise problem, an efficient expanded …
efficient arithmetic operations. To overcome the noise problem, an efficient expanded …
FPGA realization of a speech encryption system based on a generalized modified chaotic transition map and bit permutation
This paper proposes a generalized modified chaotic transition map with three independent
parameters. A hardware speech encryption scheme utilizing this map along with a bit …
parameters. A hardware speech encryption scheme utilizing this map along with a bit …
An efficient VLSI architecture design for logarithmic multiplication by using the improved operand decomposition
Over the last few years, the Logarithmic Number System (LNS) has played a pivotal and
decisive role in the field of Digital Signal Processing (DSP) and Image processing …
decisive role in the field of Digital Signal Processing (DSP) and Image processing …
A review of approximate multipliers and its applications
E Jagadeeswara Rao, P Samundiswary - International Conference on …, 2020 - Springer
Abstract Recently Low Power (LP) and High Speed (HS) of real-time computing is necessary
for various application areas like image processing, neural network, internet of things and …
for various application areas like image processing, neural network, internet of things and …
Optimal detection for one-shot transmission over diffusion-based molecular timing channels
Y Murin, N Farsad, M Chowdhury… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
This paper studies optimal detection for communication over diffusion-based molecular
timing (DBMT) channels. The transmitter simultaneously releases multiple information …
timing (DBMT) channels. The transmitter simultaneously releases multiple information …
A low error, hardware efficient logarithmic multiplier
LGSS Harsha, BR Jammu, N Bodasingi… - Circuits, Systems, and …, 2022 - Springer
The ever-increasing requirement for high-performance signal processing blocks in artificial
intelligence, IoT, and neural networks has rendered the Logarithmic arithmetic as front …
intelligence, IoT, and neural networks has rendered the Logarithmic arithmetic as front …
Investigation of error-tolerant approximate multipliers for image processing applications
D Tilak Raju, Y Srinivasa Rao - Communication and Intelligent Systems …, 2022 - Springer
Low-power, high-speed real-time computing is critical for various applications, with digital
signal processing (DSP), image processing, the internet of things, and neural networks …
signal processing (DSP), image processing, the internet of things, and neural networks …
Optimal detection for diffusion-based molecular timing channels
Y Murin, N Farsad, M Chowdhury… - arXiv preprint arXiv …, 2017 - arxiv.org
This work studies optimal detection for communication over diffusion-based molecular timing
(DBMT) channels. The transmitter simultaneously releases multiple information particles …
(DBMT) channels. The transmitter simultaneously releases multiple information particles …
Compact and errorless 16-region error correction scheme for antilogarithm converter
In numerous applications, the utilization of logarithm multiplier becoming popular due to
hardware efficiency and errorless design. In logarithm multiplier, an error created at the time …
hardware efficiency and errorless design. In logarithm multiplier, an error created at the time …