Efficient implementation of parallel BCD multiplication in LUT-6 FPGAs

A Vazquez, F De Dinechin - 2010 International Conference on …, 2010 - ieeexplore.ieee.org
Decimal multiplication is one of the most frequent operations used by many financial,
business and user-oriented applications but current implementations in FPGAs are very …

Improving the area of fast parallel decimal multipliers

M Véstias, H Neto - Microprocessors and Microsystems, 2018 - Elsevier
Financial and commercial applications depend on decimal arithmetic because they must
produce results that match exactly those obtained by human calculations. Decimal …

Revisiting the Newton-Raphson iterative method for decimal division

MP Vestias, HC Neto - 2011 21st International Conference on …, 2011 - ieeexplore.ieee.org
In this paper, we propose an iterative decimal divider. The divider uses the Newton-
Raphson iterative method with an initial approximation calculated with a minimax …

Efficient realization of bcd multipliers using fpgas

S Gao, D Al-Khalili, JMP Langlois… - International Journal of …, 2017 - Wiley Online Library
In this paper, a novel BCD multiplier approach is proposed. The main highlight of the
proposed architecture is the generation of the partial products and parallel binary operations …

Iterative decimal multiplication using binary arithmetic

MP Véstias, HC Neto - 2011 VII Southern Conference on …, 2011 - ieeexplore.ieee.org
The IEEE-754 2008 standard for floating point arithmetic has definitely dictated the
importance of decimal arithmetic. Human-centric applications, like financial and commercial …

Fast architecture for decimal digit multiplication

M Fazlali, H Valikhani, S Timarchi, HT Malazi - Microprocessors and …, 2015 - Elsevier
BCD digit multiplication module (BDM) is widely used in BCD arithmetic, especially in
Decimal Floating-Point (DFP) units. In this paper, we present a new BCD digit multiplication …

A new area-efficient BCD-digit multiplier

E Castillo, A Lloris, DP Morales, L Parrilla… - Digital Signal …, 2017 - Elsevier
Abstract In the Internet of Things era, with millions of devices performing financial and
commercial operations, decimal arithmetic has become very popular in the computation of …

High performance Vedic BCD multiplier and modified binary to BCD converter

AK Mehta, M Gupta, V Jain… - 2013 Annual IEEE India …, 2013 - ieeexplore.ieee.org
Decimal data processing applications have grown exponentially in recent years and the
IEEE 754-2008 standard for floating point arithmetic has already dictated the importance of …

Efficient ASIC and FPGA implementation of binary-coded decimal digit multipliers

S Gorgin, G Jaberipur, R Hashemi Asl - Circuits, Systems, and Signal …, 2014 - Springer
Partial product generation (PPG), in radix-10 multiplication hardware, is often done through
selection of pre-computed decimal multiples of the multiplicand. However, ASIC and FPGA …

A fast FPGA-based BCD adder

M Ul Haque, ZT Sworna, HM Hasan Babu… - Circuits, Systems, and …, 2018 - Springer
The binary-coded decimal (BCD) being the more accurate and human-readable
representation with ease of conversion is prevailing in the computing and electronic …