Systems and methods for facilitating low power on a network-on-chip
JA Bauman, J Rowlands, S Kumar - US Patent 10,452,124, 2019 - Google Patents
Aspects of the present disclosure are directed to a power specification and Network on Chip
(NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC …
(NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC …
System-on-chip (SoC) optimization through transformation and generation of a network-on-chip (NoC) topology
The present disclosure is directed to system-on-chip (SoC) optimization through
transformation and generation of a network-on-chip (NoC) topology. The present disclosure …
transformation and generation of a network-on-chip (NoC) topology. The present disclosure …
End-to-end quality-of-service in a network-on-chip
IA Swarbrick, Y Arbel, M Mittal, S Ahmad - US Patent 10,673,745, 2020 - Google Patents
An example method of generating a configuration for a network on chip (NoC) in a
programmable device includes: receiving traffic flow requirements for a plurality of traffic …
programmable device includes: receiving traffic flow requirements for a plurality of traffic …
Dynamic control of multi-region fabric
B Tsien, AJ Branover, AD Smith, CS Patel - US Patent 10,861,504, 2020 - Google Patents
Abstract Systems, apparatuses, and methods for implementing dynamic control of a multi-
region fabric are disclosed. A system includes at least one or more processing units, one or …
region fabric are disclosed. A system includes at least one or more processing units, one or …
Self identifying interconnect topology
V Kalyanasundharam, EC Morton, AD Smith… - US Patent …, 2021 - Google Patents
(57) ABSTRACT A system for automatically discovering fabric topology includes at least one
or more processing units, one or more memory devices, a security processor, and a …
or more processing units, one or more memory devices, a security processor, and a …
Generating physically aware network-on-chip design from a physical system-on-chip specification
R Chopra, YT Lin, S Kumar - US Patent 10,218,580, 2019 - Google Patents
Different example implementations of the present disclosure relates to methods and
computer readable mediums for automatically generating physically aware NoC design and …
computer readable mediums for automatically generating physically aware NoC design and …
Method and apparatus for in-band priority adjustment forwarding in a communication fabric
AD Smith, EC Morton, V Kalyanasundharam… - US Patent …, 2020 - Google Patents
Systems, apparatuses, and methods for implementing prior ity adjustment forwarding are
disclosed. A system includes at least one or more processing units, a memory, and a …
disclosed. A system includes at least one or more processing units, a memory, and a …
Application mapping on hardened network-on-chip (NoC) of field-programmable gate array (FPGA)
S Kumar - US Patent 11,023,377, 2021 - Google Patents
Methods and example implementations described herein are generally directed to the
addition of networks-on-chip (NoC) to FPGAs to customize traffic and optimize performance …
addition of networks-on-chip (NoC) to FPGAs to customize traffic and optimize performance …
Repository of integration description of hardware intellectual property for NoC construction and SoC integration
Methods and example implementations described herein are generally directed to
repository of integration description of hardware intellectual property (IP) for NoC …
repository of integration description of hardware intellectual property (IP) for NoC …
Automatic crossbar generation and router connections for network-on-chip (NOC) topology generation
(57) ABSTRACT A system and method for automatic crossbar generation and router
connections for Network-on-Chip (NoC) topology generation is disclosed. Aspects of the …
connections for Network-on-Chip (NoC) topology generation is disclosed. Aspects of the …