Constraint multiset grammars provide a general, high-level framework for the definition of
visual languages. They are a new formalism based on multiset rewriting. We give a formal …

A large scale, cache-based multiprocessor that is interconnected by a hierarchical network
such as hierarchical buses or a multistage interconnection network (MIN) is considered. An …

We describe a simulator which emulates the activity of a shared memory, common bus
multiprocessor system with private caches. Both kernel and user program activities are …

Parallel applications differ from significant bus traffic due to the transfer of shared data.
Large block sizes exploit locality and decrease the effective memory access time. It also has …

In this paper we examine the effect of skewed access on the buffer hit ratio in a multi-system
data sharing environment, where each computing node has access to shared data on disks …

This paper introduces an innovative cache design for vector computers, called prime-
mapped cache. By utilizing the special properties of a Mersenne prime, the new design does …

57 ABSTRACT A cache memory system for use during vector process ing in a processor.
The processor contains a central processing unit (CPU) and a main memory. The system …

The following study shows a direct comparison of memory write policies in Shared Memory
Multicore Systems. Although there are much work and many studies about this issue, our …

Six buffer coherency policies for a multisystem transaction processing environment are
compared. These policies differ in their basic approaches on how and when the invalidated …

As microprocessor speeds continue to improve at a very fast rate the bandwidth
requirements for system level interconnections in multiprocessors may eventually rule out …