A highly CMOS compatible hafnia-based ferroelectric diode

Q Luo, Y Cheng, J Yang, R Cao, H Ma, Y Yang… - Nature …, 2020 - nature.com
Memory devices with high speed and high density are highly desired to address the
'memory wall'issue. Here we demonstrated a highly scalable, three-dimensional stackable …

Semiconductor-metal transition caused by increased surface charge in two-dimensional quintuple-layers Al2O3 materials

X Wang, J Xu, J Si, B Wang, W Yin - Applied Surface Science, 2023 - Elsevier
Abstract Two-dimensional (2D) quintuple-layer (QL) Al 2 O 3 with intrinsic out-of-plane
polarization exhibit many interesting physical properties. We systematically study the …

Holistic optimization of trap distribution for performance/reliability in 3-D NAND flash using machine learning

K Nam, C Park, H Yun, JS Yoon, H Jang, K Cho… - IEEE …, 2023 - ieeexplore.ieee.org
A machine learning (ML) method was used to optimize the trap distribution of the charge trap
nitride (CTN) to simultaneously improve its performance/reliability (P/R) characteristics …

Investigation and modeling of Z-interference in poly-Si channel-based 3-D NAND flash memories

H Jo, S Ahn, H Shin - IEEE Transactions on Electron Devices, 2022 - ieeexplore.ieee.org
In this article, the Z-interference in 3-D charge trap nitride (CTN) NAND flash memory is
investigated using technology computer-aided design (TCAD) simulation. In 3-D CTN NAND …

Origin of incremental step pulse programming (ISPP) slope degradation in charge trap nitride based multi-layer 3D NAND flash

K Nam, C Park, JS Yoon, H Jang, MS Park, J Sim… - Solid-State …, 2021 - Elsevier
Abstract We analyzed Incremental Step Pulse Programming (ISPP) slope degradation to
improve the program efficiency of 3D NAND Flash memory using both measurement and …

Electron transport mechanism through ultrathin Al2O3 films grown at low temperatures using atomic–layer deposition

P Ma, W Guo, J Sun, J Gao, G Zhang… - Semiconductor …, 2019 - iopscience.iop.org
Abstract Alumina (Al 2 O 3) films of different thicknesses have been grown at different low
temperatures (100 C–250 C) by atomic–layer deposition on n–type Si substrate. The …

Influence of channel hole remaining ratio on hemi-cylindrical vertical NAND flash memory

JH Chang, JH Uhm, HS Kwon, E Kwon… - IEEE Electron Device …, 2022 - ieeexplore.ieee.org
The influence of the channel hole remaining ratio (CHRR) on the hemi-cylindrical (HC)
vertical NAND (VNAND) flash memory was investigated using both simulation and …

Inert ambient annealing effect on MANOS capacitor memory characteristics

N Nikolaou, P Dimitrakis, P Normand… - …, 2015 - iopscience.iop.org
In this work we report on the influence of nitrogen ambient thermal effects on the
performance of Pt/Al 2 O 3/Si 3 N 4/SiO 2/Si memory capacitors. Two post deposition …

Analysis and compact modeling of fast detrapping from bandgap-engineered tunneling oxide in 3-D NAND flash memories

M Kim, H Shin - IEEE Transactions on Electron Devices, 2021 - ieeexplore.ieee.org
We present the comprehensive analysis and the compact modeling methodology of fast
electron detrapping from the bandgap engineered tunneling oxide (BE-TOX) in 3-D NAND …

Influence of intercell trapped charge on vertical NAND flash memory

WY Choi, HS Kwon, YJ Kim, B Lee… - IEEE Electron …, 2016 - ieeexplore.ieee.org
The influence of intercell trapped charge (ITC)—the charge trapped at the inter-cell nitride
regions by fringe electric fields during program and erase operations—on vertical NAND …