A script-based cycle-true verification framework to speed-up hardware and software co-design: Performance evaluation on ecc accelerator use-case

L Zulberti, S Di Matteo, P Nannipieri, S Saponara… - Electronics, 2022 - mdpi.com
Digital designs complexity has exponentially increased in the last decades. Heterogeneous
Systems-on-Chip integrate many different hardware components which require a reliable …

BRISC-V: An open-source architecture design space exploration toolbox

S Bandara, A Ehret, D Kava, MA Kinsy - arXiv preprint arXiv:1908.09992, 2019 - arxiv.org
In this work, we introduce a platform for register-transfer level (RTL) architecture design
space exploration. The platform is an open-source, parameterized, synthesizable set of RTL …

Fast and cycle-accurate emulation of large-scale networks-on-chip using a single fpga

TV Chu, S Sato, K Kise - ACM Transactions on Reconfigurable …, 2017 - dl.acm.org
Modeling and simulation/emulation play a major role in research and development of novel
Networks-on-Chip (NoCs). However, conventional software simulators are so slow that …

Hermes: Secure heterogeneous multicore architecture design

MA Kinsy, S Khadka, M Isakov… - 2017 IEEE International …, 2017 - ieeexplore.ieee.org
The emergence of general-purpose system-on-chip (SoC) architectures has given rise to a
number of significant security challenges. The current trend in SoC design is system-level …

[PDF][PDF] 新型高性能计算系统与技术

廖湘科, 肖侬 - 中国科学: 信息科学, 2016 - scis.scichina.com
摘要高性能计算技术是信息时代世界各国特别是发达国家激烈竞争的技术制高点.
本文针对未来新型高性能计算技术的挑战, 从微处理器, 高性能计算机系统 …

Soccom: Automated synthesis of system-on-chip architectures

APD Nath, K Raj, S Bhunia… - IEEE Transactions on Very …, 2022 - ieeexplore.ieee.org
We present CAD framework and EDA tool,, for automated synthesis of optimized SoC
architectures. We delineate a disciplined and streamlined methodology to enable automated …

Dovado: An open-source design space exploration framework

D Paletti, D Conficconi… - 2021 IEEE International …, 2021 - ieeexplore.ieee.org
Traditional hardware development exploits description languages such as VHDL and
(System) Verilog to produce highly parametrizable RTL designs. Different parameter values …

Hardware-based parallelism scheme for image steganography speed up

SH Seyed Dizaji, M Zolfy Lighvan… - … Conference on Innovative …, 2021 - Springer
Steganography is the art of concealing a document in another one. The main goal of
steganography is hiding the existence of a message in a communication. Some …

[HTML][HTML] Odatix: An open-source design automation toolbox for FPGA/ASIC implementation

J Saussereau, C Jego, C Leroux, JB Begueret - SoftwareX, 2025 - Elsevier
In modern hardware digital design, optimizing performance, resource utilization, and power
consumption across different technological targets remains a critical challenge. Indeed, the …

Design and Test of Offset Quadrature Phase-Shift Keying Modulator with GF180MCU Open Source Process Design Kit

E Mascorro-Guardado, S Ortega-Cisneros… - Electronics, 2024 - mdpi.com
This article explores the evolution of integrated circuits (IC s), highlighting the fundamental
role of open source Electronic Design Automation (EDA) tools in their development. It …