Efficient elliptic curve point multiplication using digit-serial binary field operations

GD Sutter, JP Deschamps… - IEEE Transactions on …, 2012 - ieeexplore.ieee.org
This paper details the design of a new high-speed point multiplier for elliptic curve
cryptography using either field-programmable gate array or application-specified integrated …

RTL to transistor level power modeling and estimation techniques for FPGA and ASIC: A survey

Y Nasser, J Lorandel, JC Prévotet… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
Power consumption constitutes a major challenge for electronics circuits. One possible way
to deal with this issue is to consider it very soon in the design process in order to explore …

Kina: Karatsuba initiated novel accelerator for ring-binary-lwe (rblwe)-based post-quantum cryptography

P He, Y Tu, J Xie, HS Jacinto - IEEE Transactions on Very Large …, 2023 - ieeexplore.ieee.org
Along with the National Institute of Standards and Technology (NIST) post-quantum
cryptography (PQC) standardization process, lightweight PQC-related research, and …

Modular multiplication and exponentiation architectures for fast RSA cryptosystem based on digit serial computation

GD Sutter, JP Deschamps… - IEEE Transactions on …, 2010 - ieeexplore.ieee.org
Modular exponentiation with large modulus and exponent, which is usually accomplished by
repeated modular multiplications, has been widely used in public key cryptosystems …

Multifunction residue architectures for cryptography

D Schinianakis, T Stouraitis - IEEE Transactions on Circuits and …, 2014 - ieeexplore.ieee.org
A design methodology for incorporating Residue Number System (RNS) and Polynomial
Residue Number System (PRNS) in Montgomery modular multiplication in GF (p) or GF (2 n) …

[图书][B] Guide to FPGA implementation of arithmetic functions

JP Deschamps, GD Sutter, E Cantó - 2012 - books.google.com
This book is designed both for FPGA users interested in developing new, specific
components-generally for reducing execution times–and IP core designers interested in …

RISC-V Galois field ISA extension for non-binary error-correction codes and classical and post-quantum cryptography

YM Kuo, F García-Herrero, O Ruano… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
Due to the recent advances in new communication standards, such as 5G New Radio and
beyond 5G, and in quantum computing and communications, new requirements for …

High-speed hardware architecture of scalar multiplication for binary elliptic curve cryptosystems

B Rashidi, SM Sayedi, RR Farashahi - Microelectronics journal, 2016 - Elsevier
In this paper a hardware architecture of scalar multiplication based on Montgomery ladder
algorithm for binary elliptic curve cryptography is presented. In the proposed architecture …

A survey on hardware implementations of elliptic curve cryptosystems

B Rashidi - arXiv preprint arXiv:1710.08336, 2017 - arxiv.org
In the past two decades, Elliptic Curve Cryptography (ECC) have become increasingly
advanced. ECC, with much smaller key sizes, offers equivalent security when compared to …

Unified compact ECC-AES co-processor with group-key support for IoT devices in wireless sensor networks

L Parrilla, E Castillo, JA López-Ramos… - Sensors, 2018 - mdpi.com
Security is a critical challenge for the effective expansion of all new emerging applications in
the Internet of Things paradigm. Therefore, it is necessary to define and implement different …