A survey of architectural techniques for near-threshold computing

S Mittal - ACM Journal on Emerging Technologies in Computing …, 2015 - dl.acm.org
Energy efficiency has now become the primary obstacle in scaling the performance of all
classes of computing systems. Low-voltage computing, specifically, near-threshold voltage …

Multi-layer memory resiliency

N Dutt, P Gupta, A Nicolau, A BanaiyanMofrad… - Proceedings of the 51st …, 2014 - dl.acm.org
With memories continuing to dominate the area, power, cost and performance of a design,
there is a critical need to provision reliable, high-performance memory bandwidth for …

Bacterial foraging driven exploration of multi cycle fault tolerant datapath based on power-performance tradeoff in high level synthesis

A Sengupta, S Bhadauria - Expert Systems with Applications, 2015 - Elsevier
Technology evolution and energy of particle impact both plays a major role in inducing multi-
cycle transient fault (longer duration transient) in a device. However, designing an optimized …

Energy efficiency in multicore shared cache by fault tolerance using a genetic algorithm based block reuse predictor

A Choudhury, B Mondal, K Paul, BK Sikdar - Microprocessors and …, 2023 - Elsevier
Aggressive voltage scaling to reduce energy consumption in Multicore causes exponential
cell failures in SRAM. Last-level-cache (LLC), the major contender of chip area, exhibits …

VANUCA: Enabling near-threshold voltage operation in large-capacity cache

Y Wang, Y Han, H Li, X Li - IEEE Transactions on Very Large …, 2015 - ieeexplore.ieee.org
In this paper, we investigate the feasibility of voltage adjustment in a large capacity cache,
and propose the architecture of voltage-adaptable nonuniform cache access (VANUCA) that …

Smart driver for power reduction in next generation bistable electrophoretic display technology

MA Baker, A Shrivastava, KS Chatha - Proceedings of the 5th IEEE/ACM …, 2007 - dl.acm.org
Microencapsulated electrophoretic displays (EPDs) are quickly emerging as an important
technology for use in battery-powered portable computing devices. Thanks to bistability and …

Preventing design reverse engineering with reconfigurable spin transfer torque lut gates

T Winograd, H Salmani, H Mahmoodi… - … on Quality Electronic …, 2016 - ieeexplore.ieee.org
This paper presents a rigorous step towards design-for-assurance by employing the non-
volatile spin transfer torque magnetic technology to design reconfigurable Look-Up-Tables …

NVP: Non-uniform voltage and pulse width settings for power efficient hybrid STT-RAM

RJ Behrouz, H Homayoun - International Green Computing …, 2014 - ieeexplore.ieee.org
As technology scales down, the leakage power of SRAM based cache becomes a more
critical source of power dissipation, particularly for large last level cache where leakage …

ReMiT: Redundancy migration for latency aware fault tolerant cache design in multicore

A Choudhury, B Mondal… - 2018 8th International …, 2018 - ieeexplore.ieee.org
Power dissipation in Chip Multiprocessors (CMPs) has been addressed by Dynamic Voltage
and Frequency Scaling (DVFS). But uncontrolled reduction of voltage supply results in …

Block disabling characterization and improvements in CMPs operating at ultra-low voltages

A Ferrerón, D Suarez-Gracia… - 2014 IEEE 26th …, 2014 - ieeexplore.ieee.org
Power density has become the limiting factor in technology scaling as power budget restricts
the amount of hardware that can be active at the same time. Reducing supply voltage to ultra …