Scaling beyond 7nm node: An overview of gate-all-around fets

W Hu, F Li - 2021 9th international symposium on next …, 2021 - ieeexplore.ieee.org
Gate-all-around (GAA) is a promising MOSFET structure to continue scaling down the size of
CMOS devices beyond 7 nm technology node. This paper gives an overview of different …

An investigation of linearity performance and intermodulation distortion of GME CGT MOSFET for RFIC design

P Ghosh, S Haldar, RS Gupta… - IEEE transactions on …, 2012 - ieeexplore.ieee.org
In this paper, an extensive study on the intermodulation distortion and the linearity of gate-
material-engineered cylindrical-gate MOSFET (GME CGT MOSFET) has been done, and the …

Atomic layer etching of HfO2 using sequential, self-limiting thermal reactions with Sn (acac) 2 and HF

Y Lee, JW DuMont, SM George - ECS Journal of Solid State …, 2015 - iopscience.iop.org
The atomic layer etching (ALEt) of HfO 2 was performed using sequential, self-limiting
thermal reactions with tin (II) acetylacetonate (Sn (acac) 2) and HF as the reactants. The HF …

Impact of gate material engineering (GME) on analog/RF performance of nanowire Schottky-barrier gate all around (GAA) MOSFET for low power wireless …

M Kumar, S Haldar, M Gupta, RS Gupta - Microelectronics journal, 2014 - Elsevier
Abstract In this paper Gate Material Engineered (GME) Gate-Stack (GS) silicon nanowire
Schottky-Barrier (SB) Gate All Around (GAA) MOSFET and Single Material Gate Stack …

High-K spacer dual-metal gate stack underlap junctionless gate all around (HK-DMGS-JGAA) MOSFET for high frequency applications

A Goel, S Rewari, S Verma, RS Gupta - Microsystem Technologies, 2020 - Springer
Abstract High-K Spacer based Dual-Metal Gate Stack Junctionless Gate All Around (HK-
DMGS-JGAA) MOSFET has been proposed and analyzed in this paper for high frequency …

Temperature-dependent gate-induced drain leakages assessment of dual-metal nanowire field-effect transistor—analytical model

A Goel, S Rewari, S Verma… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
In this paper, an analytical model has been proposed to evaluate the effect of temperature
on gate-induced drain leakages (GIDL) in a dual-metal nanowire field-effect transistor …

Gate-all-around nanowire MOSFET with catalytic metal gate for gas sensing applications

R Gautam, M Saxena, RS Gupta… - IEEE transactions on …, 2013 - ieeexplore.ieee.org
In this paper, gate-all-around (GAA) MOSFET with catalytic metal gate is proposed for
enhanced sensitivity of gas sensor. P-channel GAA MOSFET with palladium (Pd) metal gate …

Gate-induced drain leakage reduction in cylindrical dual-metal hetero-dielectric gate all around MOSFET

S Rewari, V Nath, S Haldar, SS Deswal… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
In this paper, an analytical model of dual-metal hetero-dielectric (DM-HD) cylindrical gate all
around (GAA) MOSFET has been proposed to address and solve a substantial issue of gate …

Physics-based analytic modeling and simulation of gate-induced drain leakage and linearity assessment in dual-metal junctionless accumulation nano-tube FET (DM …

A Goel, S Rewari, S Verma, RS Gupta - Applied Physics A, 2020 - Springer
Physics-based analytical model is proposed in this paper which analyzes the effect of
temperature, channel length and silicon film radius on gate-induced drain leakages (GIDL) …

2-D-Nonlinear electrothermal model for investigating the self-heating effect in GAAFET transistors

M Belkhiria, F Echouchene, N Jaba… - … on Electron Devices, 2021 - ieeexplore.ieee.org
The objective of the present study is to analyze the heat transfer in the gate-all-around (GAA)
MOSFETs based on the Cattaneo and Vernotte (CV) model due to the finite heat …