Toward monetary cost effective content placement in cloud centric media network

Y Jin, Y Wen, K Guan, D Kilper… - 2013 IEEE International …, 2013 - ieeexplore.ieee.org
In recent years, technical challenges are emerging on how to efficiently distribute the rapid
growing user-generated contents (UGCs) with long-tailed nature. To address this issue, we …

On the capacity of bufferless networks-on-chip

A Shpiner, E Kantor, P Li, I Cidon… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
Networks-on-Chip (NoCs) form an emerging paradigm for communications within chips. In
particular, bufferless NoCs require significantly less area and power consumption, but also …

[PDF][PDF] Expansible network-on-chip architecture

ILP Pires, MAZ Alves, LCP Albini - Advances in Electrical and Computer …, 2018 - inf.ufpr.br
Interconnection has a great importance to provide a high bandwidth communication among
parallel systems. On multi-core context, Network-on-Chip is the default intra-chip …

Performance evaluation of single-and multi-hop wireless networks-on-chip with NAS Parallel Benchmarks

AMP Amorim, PAC Oliveira, HC Freitas - Journal of the Brazilian Computer …, 2015 - Springer
Background Parallel processing in the era of many-core processors demands high-
performance networks-on-chip and parallel communication based on intra-chip message …

Method for teaching parallelism on heterogeneous many-core processors using research projects

HC de Freitas - 2013 IEEE Frontiers in Education Conference …, 2013 - ieeexplore.ieee.org
Parallel programming and parallel architectures are necessary to achieve scalability and
performance. It is difficult to evaluate when to teach parallelism and how to change the …

[PDF][PDF] FlitReduce: Improving Memory Fabric Performance via End-to-End Network Packet Compression

X Li, T Sondhi - UC Berkeley CS262A Report, 2021 - people.eecs.berkeley.edu
New technologies in fabrication and packaging have led to an explosion in core counts as
time continues. Networkon-Chip (NOC) is a router-based packet switching network that …

Adaptive time-triggered network-on-chip-based multi-core architecture: enhancing safety and energy efficiency

AN Rakotojaona - 2024 - dspace.ub.uni-siegen.de
Real-time computing systems are designed to meet strict timing constraints and respond to
events or inputs within specified deadlines. These systems are commonly used in safety …

Implementation of Regular Topologies for NoCs Based on schoolMIPS Soft-Processor Cores

MY Romashikhin - 2024 International Russian Smart Industry …, 2024 - ieeexplore.ieee.org
This article describes the implementation of regular topologies for networks-on-chip. The
complexity of network development and its main parameters depend on the choice of …

A practical NoC design for parallel DES computation

R Yuan, SJ Ruan, J Götze - 2013 International Symposium …, 2013 - ieeexplore.ieee.org
The Network-on-Chip (NoC) is considered to be a new SoC paradigm for the next
generation to support a large number of processing cores. The idea to combine NoC with …

Compiler-based approach to reducing leakage energy of instruction scratch-pad memories

Y Huangfu, W Zhang - 2013 IEEE 31st International …, 2013 - ieeexplore.ieee.org
In this paper, we study a compiler-based approach to reducing the instruction SPM leakage
energy efficiently, which can also minimize the performance overhead. Our evaluation …