A 30-GHz class-F quadrature DCO using phase shifts between drain–gate–source for low flicker phase noise and I/Q exactness

X Chen, Y Hu, T Siriburanon, J Du… - Ieee Journal of Solid …, 2023 - ieeexplore.ieee.org
In this article, we present a low phase noise (PN) mm-wave quadrature digitally controlled
oscillator (DCO) exploiting transformers for class-F operation and harmonic extraction. A …

Enhanced jitter analysis and minimization for digital PLLs with mid-rise TDCs and its impact on output phase noise

X Wang, MP Kennedy - … Transactions on Circuits and Systems I …, 2023 - ieeexplore.ieee.org
Bang-bang digital phase locked loops (BBDPLL's) use a binary phase detector (BPD) to limit
the complexity and consumption of area and power of the time-to-digital converter (TDC) …

Analyses Concerning the Phase Noise and Nonlinear Behavior of the Charge-Sharing Integrator-Based Hybrid PLL

J Song, X Yang, J Liu, Y Liu, Z Zhu… - … on Circuits and …, 2024 - ieeexplore.ieee.org
Hybrid PLLs (HPLLs) leverage the advantages of conventional analog and digital PLLs to
cater to the high integration demand inherent with the advanced CMOS nodes, among …

Nonlinearity-Induced Spur Analysis in Fractional-N Synthesizers With ΔΣ Quantization Cancellation

Y Hu, W Tao, RB Staszewski - IEEE Open Journal of the Solid …, 2024 - ieeexplore.ieee.org
A fractional-N frequency synthesizer with low total jitter eg,< 50 fsrms, accounting for both
phase noise (PN) and spurs is essential for enabling the emerging 5G/6G and other high …

Computationally-Efficient Linear Periodically Time-Variant Digital PLL Modeling Using Conversion Matrices and Uncorrelated Upsampling

H Lu, PP Mercier - arXiv preprint arXiv:2401.13897, 2024 - arxiv.org
This paper introduces a conversion matrix method for linear periodically time-variant (LPTV)
digital phase-locked loop (DPLL) phase noise modeling that offers precise and …

Phase Noise Analysis for Stochastically Injected Oscillators

J Shin, WS Choi - IEEE Transactions on Circuits and Systems II …, 2023 - ieeexplore.ieee.org
For energy-efficient low-noise clock generation, many multiplying delay-locked loops or
injection-locked clock multipliers adopt probabilistic gating to calibrate circuit nonidealities …

A 4.5-5.4 GHz Digital Bang-Bang PLL for Cryogenic Applications

H Gao, H Xu, X Lin, Y Liu, Z Tang, X Kou… - 2023 IEEE …, 2023 - ieeexplore.ieee.org
This paper introduces a 4.5 G~ 5.4 GHz digital bang-bang PLL for 77K cryogenic
applications. The digital approach overcomes the design challenges that arise from a wide …

A 6.8GHz -269.9 FOMJitter-N-Area Fractional-N Pulse Shaper Based PLL with Range Extension DTC

H Gao, Y Liu, P Wu, J Liu, Y Mao… - 2024 IEEE European …, 2024 - ieeexplore.ieee.org
This paper presents a 6.8 GHz compact digital fractional-N PLL based on pulse-shaped loop
filter, where a much wider bandwidth beyond the traditional limit can be used to suppress …

Digitally Intensive RF/Millimetre-Wave Frequency Generation Techniques

X Chen - 2022 - researchrepository.ucd.ie
The advanced wireless communication standards (eg, 5G) placed stringent specifications on
the RF/mm-wave transceivers. As a main contributor to the total error vector magnitude …

Linear Periodically Time-Variant Digital PLL Phase Noise Modeling Using Conversion Matrices and Uncorrelated Upsampling

H Lu, PP Mercier - IEEE Transactions on Circuits and Systems I …, 2024 - ieeexplore.ieee.org
This paper introduces a conversion matrix method for linear periodically time-variant (LPTV)
digital phase-locked loop (DPLL) phase noise modeling that offers precise and …