A conventional figure-of-merit (FOM) for a phase-locked loop (PLL) has served as the most
powerful indicator to compare and to normalize performance of different PLL designs …

This article presents the first cryogenic phase-locked loop (PLL) operating at 4.2 K. The PLL
is designed for the control system of scalable quantum computers. The specifications of PLL …

This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL).
A charge-domain sub-sampling phase detector is introduced to achieve a high phase …

This article analyzes the jitter-power tradeoff in multiplying delay-locked loops (MDLLs),
which differs from the more typical phase-locked loop one, and identifies a design …

This paper presents a ring-type, digitally controlled oscillator (DCO)-based integer-N digital
phase-locked loop (DPLL) that can achieve low jitter and low reference spur concurrently. In …

Implementation of low-noise power-efficient clock multipliers requires low-noise high-
frequency reference clocks. This paper presents ways to generate such reference clocks at …

An injection-locked local oscillator (LO) generation targeting mm-wave multiband 5G
communication is presented. With a band-selective injection-locked frequency multiplier …

Sub-sampling PLLs (SSPLLs) are popular for generating low-jitter output signals. However,
the critical problem of SSPLLs is that they do not use a frequency divider, so the lock-in …

This paper presents an ultra-low power digitally-assisted analog ring phase-locked loop
(PLL) with a tunable switched capacitor loop filter. The PLL achieves a power efficiency of …

A fractional-phase-locked loop (PLL) architecture incorporates a switched-current finite
impulse response (FIR) filter to suppress the modulator () noise. Using a compact, low …