The expanding gap between microprocessor and DRAM performance has necessitated the
use of increasingly aggressive techniques designed to reduce or hide the latency of main …

The most exciting development in parallel computer architecture is the convergence of
traditionally disparate approaches on a common machine structure. This book explains the …

Since the introduction of virtual memory demand-paging and cache memories, computer
systems have been exploiting spatial and temporal locality to reduce the average latency of …

For decades, the serialization constraints imposed by true data dependences have been
regarded as an absolute limit-the dataflow limit-on the parallel execution of serial programs …

This paper makes the case that pin bandwidth will be a critical consideration for future
microprocessors. We show that many of the techniques used to tolerate growing memory …

In response to increasing (relative) wire delay, architects have proposed various
technologies to manage the impact of slow wires on large uniprocessor L2 caches. Block …

We introduce a dynamic scheme that captures the accesspat-terns of linked data structures
and can be used to predict future accesses with high accuracy. Our technique exploits the …

Current data cache organizations fail to deliver high performance in scalar processors for
many vector applications. There are two main reasons for this loss of performance: the use …

In emerging and future high-end processor systems, tolerating increasing cache miss
latency and properly managing memory bandwidth will be critical to achieving high …

Most previous research into vector architectures has concentrated on supercomputing
applications and small enhancements to existing vector supercomputer implementations …