Design Approaches of Ultra-Low Power SAR ADC for Biomedical Systems—A Review

K Aneesh, G Manoj, S Shylu Sam - Journal of Circuits, Systems and …, 2022 - World Scientific
In recent years, implantable biomedical devices like cardiac pacemaker, defibrillators,
cochlear implants, visual prosthesis etc. have gained immense importance in the personal …

Low-power pulse-triggered flip-flop design with conditional pulse-enhancement scheme

YT Hwang, JF Lin, MH Sheu - IEEE transactions on very large …, 2011 - ieeexplore.ieee.org
In this paper, a novel low-power pulse-triggered flip-flop (FF) design is presented. First, the
pulse generation control logic, an and function, is removed from the critical path to facilitate a …

An Overview of Low-Power VLSI Design Methods for CMOS and CNTFET-Based Circuits

A Karthik, N Domala, GS Kumar - … International Conference on …, 2023 - ieeexplore.ieee.org
Currently, the power consumption is one of the major concerns in VLSI circuit design based
on CMOS (Complementary Metal Oxide Semiconductor) and CNTFET (Carbon Nano Tube …

Optimization of web service-based control system for balance between network traffic and delay

C Hou, Q Zhao - IEEE Transactions on Automation Science and …, 2017 - ieeexplore.ieee.org
In Internet of Things systems, Web services enable interoperable machine-to-machine
communication over networks. Polling mechanism is a practical way for a Web service …

Design and comparative analysis of D-Flip-flop using conditional pass transistor logic for high-performance with low-power systems

R Murugasami, US Ragupathy - Microprocessors and Microsystems, 2019 - Elsevier
Flip-flop is one of the essential elements of data path structure design in the digital era. In
this paper, the peculiar Flip-flop topologies, called as Conditional Pass Logic Static D-Flip …

Low-power redundant-transition-free TSPC dual-edge-triggering flip-flop using single-transistor-clocked buffer

Z Wang, P Zhao, T Springer, C Zhu… - … Transactions on Very …, 2023 - ieeexplore.ieee.org
In the modern graphics processing unit (GPU)/artificial intelligence (AI) era, flip-flop (FF) has
become one of the most power-hungry blocks in processors. To address this issue, a novel …

[PDF][PDF] Low power techniques for digital system design

G Verma, M Kumar, V Khare - Indian Journal of Science and …, 2015 - researchgate.net
The proliferation of reconfigurable hardware like (FPGAs) put a challenge in front of
designers to implement fast and low powered digital designs. Main drawbacks of FPGAs are …

[HTML][HTML] Novel low-complexity and low-power flip-flop design

JF Lin, ZJ Hong, CM Tsai, BC Wu, SW Yu - Electronics, 2020 - mdpi.com
In this paper, a compact and low-power true single-phase flip-flop (FF) design with fully static
operations is presented. The design is developed by using various circuit-reduction …

Design of implicit pulsed-dual edge triggering flip flop for low power and high speed clocking systems

P Nagarajan, NA Kumar, PV Ramana - International Journal of …, 2020 - World Scientific
The flip-flops are considered as major contributors to the power dissipation of the clocking
system, which is made up of the clock provision network and storage elements (latches, flip …

A high performance D-flip flop design with low power clocking system using MTCMOS technique

P Dobriyal, K Sharma, M Sethi… - 2013 3rd IEEE …, 2013 - ieeexplore.ieee.org
Power consumption plays an important role in any integrated circuit and is listed as one of
the top three challenges in International technology roadmap for semiconductors. In any …