A carbon nano-tube field effect transistor based stable, low-power 8T static random access memory cell with improved write access time

A Sachdeva, D Kumar, E Abbasian - AEU-International Journal of …, 2023 - Elsevier
Carbon nanotube field effect transistor (CNTFET) is swiftly becoming an alternative to
conventional CMOS transistors due to superior transport properties, improved current …

Ultra-low-power and stable 10-nm FinFET 10T sub-threshold SRAM

E Abbasian, S Birla, M Gholipour - Microelectronics Journal, 2022 - Elsevier
This paper explores an ultra-low-power 10T subthreshold SRAM with high stabilities based
on 10-nm FinFETs. To prove the superiority of the proposed 10T SRAM's performance, a …

A cntfet based bit-line powered stable sram design for low power applications

A Sachdeva, L Gupta, K Sharma… - ECS Journal of Solid …, 2023 - iopscience.iop.org
Higher charge mobility, gate control, and better electrostatics are the key reasons that make
carbon nanotube field effect transistor (CNTFET) a better candidate to become the …

Design of a stable single sided 11t static random access memory cell with improved critical charge

A Sachdeva - International Journal of Numerical Modelling …, 2023 - Wiley Online Library
Radiation‐induced soft errors are becoming a key challenge in satellite‐based
communication. The worst‐hit component of such devices is static random‐access memory …

Design of a soft error hardened SRAM cell with improved access time for embedded systems

VK Tomar, A Sachdeva - Microprocessors and Microsystems, 2022 - Elsevier
Recent advancements in high-performance processor operation have nurtured the
requirement of low power, reliable, and fast static random-access memory (SRAM). Scaling …

Characterization of stable 12T SRAM with improved critical charge

A Sachdeva, VK Tomar - Journal of circuits, Systems and computers, 2022 - World Scientific
With the aggressive growth of the internet of things-based applications in the domestic and
industrial domain, the embedded static memory is also under renovation stage to eliminate …

Low power static random-access memory cell design for mobile opportunistic networks sensor nodes

A Sachdeva - Journal of Circuits, Systems and Computers, 2023 - World Scientific
In the present scenario, the devices supporting neighbor discovery are going through the
renovation phase, and crossing the classical barrier such as the trade-off between power …

Construction Technique and Evaluation of High Performance -bit Burst Error Correcting Codes for Protecting MCUs

RK Maity, J Samanta, J Bhaumik - Journal of Circuits, Systems and …, 2023 - World Scientific
The occurrences of Multiple Cell Upset (MCU) are more liable to arise in modern memory
systems with the continuous upgradation of microelectronics technology from micron to deep …

Comparative Validation of SRAM Cells Based on Decoupled Read Technique using 45nm CMOS

B Saranga, L Gupta, A Sachdeva… - 2023 IEEE 12th …, 2023 - ieeexplore.ieee.org
The modern era expects great computing power, portability, and minimal power
consumption from all electronic devices. SRAM is widely valued in the consumer electronics …

A variation tolerant nanoscale SRAM for low power wireless sensor nodes

V Bhatnagar, MK Pandey, S Pandey - Wireless Personal Communications, 2022 - Springer
A novel read circuit for low power dual bit-line SRAM is proposed. The local sensing circuit
uses differential cell current and regenerative feedback to turn into latch. This allows lower of …