Physical design obfuscation of hardware: A comprehensive investigation of device and logic-level techniques

A Vijayakumar, VC Patil, DE Holcomb… - IEEE Transactions …, 2016 - ieeexplore.ieee.org
The threat of hardware reverse engineering is a growing concern for a large number of
applications. A main defense strategy against reverse engineering is hardware obfuscation …

CMP fill synthesis: A survey of recent studies

AB Kahng, K Samadi - Handbook of Algorithms for Physical …, 2008 - taylorfrancis.com
Chemical–mechanical polishing (CMP) is the planarizing technique of choice to satisfy the
local and global planarity constraints imposed by advanced lithography methods. The …

Crosstalk-induced delay, noise, and interconnect planarization implications of fill metal in nanoscale process technology

A Nieuwoudt, J Kawa… - IEEE transactions on very …, 2009 - ieeexplore.ieee.org
In this paper, we investigate the crosstalk-induced delay, noise, and chemical mechanical
polishing (CMP)-induced thickness-variation implications of dummy fill generated using rule …

Efficient approximation algorithms for chemical mechanical polishing dummy fill

C Feng, H Zhou, C Yan, J Tao… - IEEE Transactions on …, 2011 - ieeexplore.ieee.org
To reduce chip-scale topography variation in chemical mechanical polishing process,
dummy fill is widely used to improve the layout density uniformity. Previous researches …

PushPull: Short path padding for timing error resilient circuits

YM Yang, IHR Jiang, ST Ho - Proceedings of the 2013 ACM International …, 2013 - dl.acm.org
Modern IC designs are exposed to a wide range of dynamic variations. Traditionally, a
conservative timing guardband is required to guarantee correct operations under the worst …

Accurate closed-form capacitance extraction formulas for metal fill in RFICs

SG Gaskill, VS Shilimkar… - 2009 IEEE Radio …, 2009 - ieeexplore.ieee.org
Metal fill patterning in modern IC processes forces many floating metal structures to exist in
the fabricated design. The number of these structures makes electrostatic capacitance …

[HTML][HTML] A Deep Learning Approach for Efficient Electromagnetic Analysis of On-Chip Inductor with Dummy Metal Fillings

X Li, Y Tang, P Zhao, S Chen, K Xu, G Wang - Electronics, 2022 - mdpi.com
A deep learning approach for the efficient electromagnetic analysis of an on-chip inductor
with dummy metal fillings (DMFs) is proposed. By comparing different activation functions …

DOE-based extraction of CMP, active and via fill impact on capacitances

AB Kahng, RO Topaloglu - IEEE transactions on …, 2008 - ieeexplore.ieee.org
Chemical-mechanical polishing (CMP), active and via fills have become indispensable
aspects of semiconductor manufacturing. CMP fills are used to reduce metal thickness …

Impact of dummy filling techniques on interconnect capacitance and planarization in nano-scale process technology

A Nieuwoudt, J Kawa, Y Massoud - Proceedings of the 18th ACM Great …, 2008 - dl.acm.org
As process technology continues to scale into the nanometer regime, the interplay between
dummy fill metal placement and interconnect thickness variation due to chemical …

Investigating the impact of fill metal on crosstalk-induced delay and noise

A Nieuwoudt, J Kawa… - … Symposium on Quality …, 2008 - ieeexplore.ieee.org
In this paper, we investigate the crosstalk-induced delay and noise implications of floating
and grounded fill metal generated using each of the rule-based and model-based fill …