A survey of on-chip optical interconnects

J Bashir, E Peter, SR Sarangi - ACM Computing Surveys (CSUR), 2019 - dl.acm.org
Numerous challenges present themselves when scaling traditional on-chip electrical
networks to large manycore processors. Some of these challenges include high latency …

Optics in computing: From photonic network-on-chip to chip-to-chip interconnects and disintegrated architectures

T Alexoudi, N Terzenidis, S Pitris… - Journal of Lightwave …, 2018 - ieeexplore.ieee.org
Following a decade of radical advances in the areas of integrated photonics and computing
architectures, we discuss the use of optics in the current computing landscape attempting to …

Suor: Sectioned undirectional optical ring for chip multiprocessor

X Wu, J Xu, Y Ye, Z Wang, M Nikdast… - ACM Journal on Emerging …, 2014 - dl.acm.org
Chip multiprocessor (CMP) is becoming an attractive platform for applications seeking both
high performance and high energy efficiency. In large-scale CMPs, the communication …

Systematic analysis of crosstalk noise in folded-torus-based optical networks-on-chip

M Nikdast, J Xu, X Wu, W Zhang, Y Ye… - … on Computer-Aided …, 2014 - ieeexplore.ieee.org
Photonic devices are widely used in optical networks-on-chip (ONoCs) and suffer from
crosstalk noise. The accumulative crosstalk noise in large scale ONoCs diminishes the …

Towards efficient on-chip communication: A survey on silicon nanophotonics and optical networks-on-chip

UU Nisa, J Bashir - Journal of Systems Architecture, 2024 - Elsevier
Silicon nanophotonics, with its high-speed, low-loss optical interconnects, and high
computation capabilities, is seen as one of the promising technologies that can easily …

Flat-topology high-throughput compute node with AWGR-based optical-interconnects

P Grani, R Proietti, S Cheung, SJB Yoo - Journal of Lightwave …, 2016 - opg.optica.org
This study presents simulation studies on the execution time and energy consumption of
optical multi-socket boards with on-chip, all-to-all, and contention-less arrayed waveguide …

Chameleon: Channel efficient optical network-on-chip

S Le Beux, H Li, I O'Connor, K Cheshmi… - … , Automation & Test …, 2014 - ieeexplore.ieee.org
The next generation of MPSoC points to the integration of thousands of IP cores, requiring
high performance interconnect for high throughput communications. Optical on-chip …

TRINE: A Tree-Based Silicon Photonic Interposer Network for Energy-Efficient 2.5 D Machine Learning Acceleration

E Taheri, MA Mahdian, S Pasricha… - Proceedings of the 16th …, 2023 - dl.acm.org
2.5 D chiplet systems have showcased low manufacturing costs and modular designs for
machine learning (ML) acceleration. Nevertheless, communication challenges arise from …

Crosstalk-aware automated mapping for optical networks-on-chip

E Fusella, A Cilardo - 2016 - dl.acm.org
Optical networks-on-chip (NoCs) provide a promising answer to address the increasing
requirements of ultra-high bandwidth and extremely low power consumption. Designing a …

H2ONoC: A Hybrid Optical–Electronic NoC Based on Hybrid Topology

E Fusella, A Cilardo - IEEE Transactions on Very Large Scale …, 2016 - ieeexplore.ieee.org
Next-generation chip multiprocessors will require communication performance levels that
cannot be achieved by traditional electronic ON-chip interconnects. Silicon photonics has …