Self-adaptive systems (SASs) are designed to handle changes and uncertainties through a
feedback loop with four core functionalities: monitoring, analyzing, planning, and execution …

The automatic generation of RTL code (eg, Verilog) using natural language instructions and
large language models (LLMs) has attracted significant research interest recently. However …

As the ubiquity and complexity of system-on-chip (SoC) designs increase across electronic
devices, incorporating security into an SoC design flow poses significant challenges …

This paper presents RTLFixer, a novel framework enabling automatic syntax errors fixing for
Verilog code with Large Language Models (LLMs). Despite LLM's promising capabilities …

Driven by Moore's Law, the complexity and scale of modern chip design are increasing
rapidly. Electronic Design Automation (EDA) has been widely applied to address the …

Many networking tasks now employ deep learning (DL) to solve complex prediction and
optimization problems. However, current design philosophy of DL-based algorithms entails …

Chip design is about to be revolutionized by the integration of large language, multimodal,
and circuit models (collectively LxMs). While exploring this exciting frontier with tremendous …

Assertion-based verification (ABV) is a critical method for ensuring design circuits comply
with their architectural specifications, which are typically described in natural language. This …

In the domain of chip design, Hardware Description Languages (HDLs) play a pivotal role.
However, due to the complex syntax of HDLs and the limited availability of online resources …

Existing large language models (LLMs) for register transfer level code generation face
challenges like compilation failures and suboptimal power, performance, and area (PPA) …