Methods for fault tolerance in networks-on-chip
Networks-on-Chip constitute the interconnection architecture of future, massively parallel
multiprocessors that assemble hundreds to thousands of processing cores on a single chip …
multiprocessors that assemble hundreds to thousands of processing cores on a single chip …
Analytical fault tolerance assessment and metrics for TSV-based 3D network-on-chip
Reliability is one of the most challenging problems in the context of three-dimensional
network-on-chip (3D NoC) systems. Reliability analysis is prominent for early stages of the …
network-on-chip (3D NoC) systems. Reliability analysis is prominent for early stages of the …
Fault-aware routing approach for mesh-based Network-on-Chip architecture
Aggressive communication among cores in multi-core architectures leads to excessive
workload on the components which often degrades the normal functionality and induces …
workload on the components which often degrades the normal functionality and induces …
Tsv-to-tsv inductive coupling-aware coding scheme for 3d network-on-chip
A Eghbal, PM Yaghini, SS Yazdi… - … Symposium on Defect …, 2014 - ieeexplore.ieee.org
A reliable Three Dimensional Network-on-Chip (3D NoC) is required for future many-core
systems. Through-silicon Via (TSV) is the prominent component of 3D NoC to support better …
systems. Through-silicon Via (TSV) is the prominent component of 3D NoC to support better …
On the design of hybrid routing mechanism for mesh-based network-on-chip
Efficient on-chip communication is necessary for exploiting enormous computing power
available on a many-core chip. Routing algorithms play a major role for the communication …
available on a many-core chip. Routing algorithms play a major role for the communication …
Reconfigurable NoC development with fault mitigation
E Suvorova, Y Sheynin… - 2016 18th Conference of …, 2016 - ieeexplore.ieee.org
An ability of faults mitigation becomes one of the main requirements for network-on-chip
(NoC) embedded systems that are manufactured with thin design rules. Other requirements …
(NoC) embedded systems that are manufactured with thin design rules. Other requirements …
A gals router for asynchronous network-on-chip
A scalable asynchronous NoC router with lower power consumption and latency comparing
to a synchronous design is introduced in this article. It employs GALS interfaces …
to a synchronous design is introduced in this article. It employs GALS interfaces …
Coupling mitigation in 3-D multiple-stacked devices
A 3-D multiple-stacked IC has been proposed to support energy efficiency for data center
operations as dynamic RAM (DRAM) scaling improves annually. 3-D multiple-stacked IC is a …
operations as dynamic RAM (DRAM) scaling improves annually. 3-D multiple-stacked IC is a …
Bio-inspired online fault detection in noc interconnect
M McElholm, J Harkin, L McDaid, S Carrillo - Energy-efficient fault-tolerant …, 2014 - Springer
Technology scaling over the years has enabled the integration of multiple processing cores
on a single chip with Network-on-chip (NoC) becoming an interconnect standard for …
on a single chip with Network-on-chip (NoC) becoming an interconnect standard for …
Falp: A fault adaptive and low power method for network on chip router
F Mohammadian - ARCS 2014; 2014 Workshop Proceedings …, 2014 - ieeexplore.ieee.org
Network-on-Chip (NoC) are known as the future communication infrastructure for many-core
systems. They are susceptible to malfunction in the presence of the faults as technology …
systems. They are susceptible to malfunction in the presence of the faults as technology …