This paper proposes a novel programmable vision chip based on multiple levels of parallel
processors. The chip integrates CMOS image sensor, multiple-levels of SIMD parallel …

A programmable vision chip for real-time vision applications is presented. The chip
architecture is a combination of a SIMD processing element array and row-parallel …

In this paper, we study a class of discrete-time fuzzy BAM neural networks with variable
delays and impulses. Based on M-matrix theory and analytic methods, some sufficient …

This paper proposes a heterogeneous parallel processor for high-speed vision chip. It
contains four levels of processors with different parallelisms and complexities: processing …

In this work we present an ultra low energy,'on-sensor'image processing architecture, based
on cellular network of spin based neurons. The'neuron'constitutes of a lateral spin valve …

A new model of cellular neural networks (CNNs) with transient chaos is proposed by adding
negative self-feedbacks into CNNs after transforming the dynamic equation to discrete time …

A programmable vision chip with variable resolution and row-pixel-mixed parallel image
processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit …

This paper introduces a binary‐based on‐chip cellular neural network (CNN) solution for
pixel‐level snakes. Every cell in the array comprises circuitry for B/W and grey‐scale …

This paper addresses the extension of applications covered by binary CNN-based
architectures. The work is focused on diffusion-like tasks on binary images, traditionally …

This letter discusses the complete stability of discrete-time cellular neural networks with
piecewise linear output functions. Under the assumption of certain symmetry on the …