A two-dimensional mesh-connected processor array is an extensively investigated
architecture used in parallel processing. Massive studies have addressed the use of …

Reducing the interconnection length of VLSI arrays leads to less capacitance, power
dissipation and dynamic communication cost between the processing elements (PEs). This …

This paper deals with the issue of developing efficient algorithms for reconfiguring two-
dimensional VLSI arrays linked by four-port switches in the presence of faulty processing …

The reconfiguration algorithms have been extensively investigated to ensure the reliability
and stability for the processor arrays with faults. It is important to reduce the power …

Reducing the number of visits to failure-free nodes can effectively reduce the reconstruction
time of logical columns and improve the reconstruction efficiency. In this paper, we describe …

Homogeneous processor arrays are emerging in tera-scale computation and effective fault
tolerance techniques are essential to improving the reliability of such complex integrated …

This paper presents novel techniques to accelerate the reconfiguration of degradable very
large scale integration arrays. A preprocessing step is used to derive the upper and lower …

Large-scale sensor-based decision support systems are being widely deployed. Assessing
the trustworthiness of sensor data and the owners of this data is critical for quality assurance …

With the increased density of three-dimensional (3D) processor arrays, faults can potentially
occur quite often due to power overheating during massively parallel computing. In order to …

With the ever-increasing integration and parallel computing capabilities of 3D processor
arrays, the occurrence of processor elements (PEs) failures caused by various factors has …