Semiconductor package and manufacturing method of the same

MF Chen, SF Yeh, CH Yu - US Patent 10,685,911, 2020 - Google Patents
The present disclosure provides a semiconductor package, including a first semiconductor
structure, a first bonding dielectric over the first semiconductor structure and surrounding a …

Semiconductor structure and manufacturing method thereof

CP Huang, HM Tu, CJ Yang, SW Liang, HY Kuo… - US Patent …, 2017 - Google Patents
(57) ABSTRACT A semiconductor structure includes a die including a die pad disposed over
the die; a conductive member disposed over and electrically connected with the die pad; a …

Integrated fan-out package with 3D magnetic core inductor

WS Liao, CH Tung, CH Yu, CP Jou… - US Patent 10,923,417, 2021 - Google Patents
Among other things, a method of fabricating an integrated electronic device package is
described. First trace portions of an electrically conductive trace are formed on an electri …

Coaxial through via with novel high isolation cross coupling method for 3D integrated circuits

FW Kuo, WS Liao, CP Jou, C Huan-Neng… - US Patent …, 2021 - Google Patents
(57) ABSTRACT A semiconductor package includes a first semiconductor device, a second
semiconductor device vertically positioned above the first semiconductor device, and a …

Stacked die semiconductor device with separate bit line and bit line bar interconnect structures

SA Chi - US Patent 10,283,171, 2019 - Google Patents
An apparatus includes a first tier, a second tier and a memory. The second tier is vertically
stacked on the first tier. The memory includes a column of memory bit cells. A first portion of …

Method for reducing contact resistance in semiconductor structures

JP Colinge, CH Diaz - US Patent 9,893,189, 2018 - Google Patents
Semiconductor structures and methods reduce contact resistance, while retaining cost
effectiveness for integration into the process flow by introducing a heavily-doped contact …

Inter-fan-out wafer level packaging with coaxial TIV for 3D IC low-noise packaging

FW Kuo, WS Liao - US Patent 10,037,897, 2018 - Google Patents
(57) ABSTRACT A semiconductor package includes a first semiconductor element, an
insulating layer, and a second semiconductor element. The first semiconductor element …

Bonding structure of dies with dangling bonds

HW Chen, MF Chen, CC Hu - US Patent 10,861,808, 2020 - Google Patents
A method includes polishing a semiconductor substrate of a first die to reveal first through-
vias that extend into the semiconductor substrate, forming a dielectric layer on the …

Input output for an integrated circuit

CM Fu - US Patent 9,773,754, 2017 - Google Patents
702/108 8, 405, 442 B2 3/2013 Chen 8, 436, 671 B2 5/2013 Chern et al. 8, 448, 100 B1
5/2013 Lin et al. 8, 610, 488 B2 12/2013 Yu et al. 8, 625, 240 B2 1/2014 Chung et al. 8, 631 …

IC degradation management circuit, system and method

PZ Kang, CH Chang, WS Chou, YC Peng - US Patent 10,222,412, 2019 - Google Patents
An IC degradation sensor is disclosed. The IC degradation management sensor includes an
odd number of first logic gates electrically connected in a ring oscillator configura tion, each …