Nanosheet FET for Future Technology Scaling
AS Kumar, VB Sreenivasulu… - … Devices for Artificial …, 2024 - Wiley Online Library
Improvements in the VLSI industry have always been striving to justify the Moore's law by
implanting, twice count transistors from the existing one. This law has made a significant …
implanting, twice count transistors from the existing one. This law has made a significant …
Design and analysis of electrostatic doped Schottky barrier CNTFET based low power SRAM
In recent years, much emphasis is given for low power memory design by reducing leakage
power. Carbon nanotube field effect transistor (CNTFET) based static random access …
power. Carbon nanotube field effect transistor (CNTFET) based static random access …
Design and analysis of dynamically configurable electrostatic doped carbon nanotube tunnel FET
This paper proposes a novel design of dynamically configurable electrostatic doped double
gate carbon nanotube tunnel FET (ED CN-TFET). The proposed device consists of intrinsic …
gate carbon nanotube tunnel FET (ED CN-TFET). The proposed device consists of intrinsic …
Improved sensitivity of dielectric modulated junctionless transistor for nanoscale biosensor design
This work has proposed a device ie, Dielectric Modulated (DM) Junctionless Transistor
which is utilizes as Label-Free (LF) electrical characteristic detection of bio-molecules. The …
which is utilizes as Label-Free (LF) electrical characteristic detection of bio-molecules. The …
Analysis of electrostatic doped Schottky barrier carbon nanotube FET for low power applications
This paper presents the analysis of electrostatic doped Schottky barrier carbon nanotube
FET (ED-SBCNTFET) for low power applications. Electrostatic doping is introduced in …
FET (ED-SBCNTFET) for low power applications. Electrostatic doping is introduced in …
Cntfet based 4-trit hybrid ternary adder-subtractor for low power & high-speed applications
To go through the phenomenon at nanoscale regimes, circuits using the CNTFETbased on
Ternary Logic have been explored due to their constantly increasing application in high …
Ternary Logic have been explored due to their constantly increasing application in high …
Graphene Nanoribbon for Future VLSI Applications: A Review
H Sharma - Integrated Devices for Artificial Intelligence and …, 2024 - Wiley Online Library
The Moore law for scaling of technological nodes has led to the major advancement in chip
design and functionality. With the downscaling of technological nodes, the efficiency of gate …
design and functionality. With the downscaling of technological nodes, the efficiency of gate …
Electrostatically doped tunnel CNTFET model for low-power VLSI circuit design
With advantages such as low sub-threshold swing, low OFF-state current and the ability to
attain a higher ON–OFF ratio, the tunnel CNTFET is one of the most comprehensively …
attain a higher ON–OFF ratio, the tunnel CNTFET is one of the most comprehensively …
Effect of doping profile variation on nanoscale cylindrical gate carbon nanotube field-effect transistor: a computational study using nonequilibrium Green's function …
The scaling down of modern devices beyond 15 nm has faced major setbacks as it
engendered short channel effects which were seemingly inexorable. One of the solutions …
engendered short channel effects which were seemingly inexorable. One of the solutions …
Ferroelectric Random Access Memory (FeRAM)
BV Reddy, T Chaudhary, M Singh… - Integrated Devices for …, 2024 - Wiley Online Library
We examine the recent development of ferroelectric memory, along with ferroelectric random
access memory (FRAM). Sophisticated non‐volatile memories including resistive random …
access memory (FRAM). Sophisticated non‐volatile memories including resistive random …