A wear leveling aware memory allocator for both stack and heap management in PCM-based main memory systems

W Li, Z Shuai, CJ Xue, M Yuan… - 2019 Design, Automation …, 2019 - ieeexplore.ieee.org
Phase change memory (PCM) has been considered as a replacement of DRAM, due to its
potentials in high storage density and low leakage power. However, the limited write …

Craft: Criticality-aware fault-tolerance enhancement techniques for emerging memories-based deep neural networks

TH Nguyen, M Imran, J Choi… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
Deep neural networks (DNNs) have emerged as the most effective programming paradigm
for computer vision and natural language processing applications. With the rapid …

Low-cost and effective fault-tolerance enhancement techniques for emerging memories-based deep neural networks

TH Nguyen, M Imran, J Choi… - 2021 58th ACM/IEEE …, 2021 - ieeexplore.ieee.org
Deep Neural Networks (DNNs) have been found to outperform conventional programming
approaches in several applications such as computer vision and natural language …

A novel ultra-low power 8T SRAM-based compute-in-memory design for binary neural networks

Y Kim, S Li, N Yadav, KK Choi - Electronics, 2021 - mdpi.com
We propose a novel ultra-low-power, voltage-based compute-in-memory (CIM) design with
a new single-ended 8T SRAM bit cell structure. Since the proposed SRAM bit cell uses a …

Heterogeneous PCM array architecture for reliability, performance and lifetime enhancement

T Kwon, M Imran, JM You… - 2018 Design, Automation & …, 2018 - ieeexplore.ieee.org
Conventional DRAM and flash memory are reaching their scaling limits thus motivating
research in various emerging memory technologies as a potential replacement. Among …

A novel BIST algorithm for low-voltage SRAM

Z Cai, Y Wang, S Liu, K Lv… - 2019 IEEE International …, 2019 - ieeexplore.ieee.org
A novel Built-In Self-Test (BIST) algorithm is proposed in this paper, which is used for testing
low-voltage SRAM. The algorithm is the improvement of March C+ algorithm, which …

[图书][B] Asynchronous On-chip Networks and Fault-tolerant Techniques

W Song, G Zhang - 2022 - taylorfrancis.com
Asynchronous On-Chip Networks and Fault-Tolerant Techniques is the first comprehensive
study of fault-tolerance and fault-caused deadlock effects in asynchronous on-chip networks …

RandShift: An energy-efficient fault-tolerant method in secure nonvolatile main memory

M Soltani, M Kamal, A Afzali-Kusha… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
In this article, we present a simple, yet energy-and area-efficient method for tolerating the
stuck-at faults caused by an endurance issue in secure-resistive main memories. In the …

Analysing emerging memory technologies for big data and signal processing applications

TC Xu, V Leppänen - 2015 Fifth International Conference on …, 2015 - ieeexplore.ieee.org
In this paper, we investigate and compare different emerging memory technologies as on-
chip cache for big data and signal processing applications. Static Random Access Memory …

Block cooperation: Advancing lifetime of resistive memories by increasing utilization of error correcting codes

MK Tavana, AK Ziabari, D Kaeli - ACM Transactions on Architecture and …, 2018 - dl.acm.org
Block-level cooperation is an endurance management technique that operates on top of
error correction mechanisms to extend memory lifetimes. Once an error recovery scheme …