SODA: Stencil with optimized dataflow architecture
Stencil computation is one of the most important kernels in many application domains such
as image processing, solving partial differential equations, and cellular automata. Many of …
as image processing, solving partial differential equations, and cellular automata. Many of …
IronMan-Pro: Multiobjective design space exploration in HLS via reinforcement learning and graph neural network-based modeling
Despite the great success of high-level synthesis (HLS) tools, we observe several
unresolved challenges: 1) the high-level abstraction of HLS programming styles sometimes …
unresolved challenges: 1) the high-level abstraction of HLS programming styles sometimes …
Polyhedral-based data reuse optimization for configurable computing
Many applications, such as medical imaging, generate intensive data traffic between the
FPGA and off-chip memory. Significant improvements in the execution time can be achieved …
FPGA and off-chip memory. Significant improvements in the execution time can be achieved …
IRONMAN GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learning
Despite the great success of High-Level Synthesis (HLS) tools, we observe several
unresolved challenges: 1) the high-level abstraction of programming styles in HLS conceals …
unresolved challenges: 1) the high-level abstraction of programming styles in HLS conceals …
Optimizing for parallelism and data locality
K Kennedy, KS McKinley - … of the 6th international conference on …, 1992 - dl.acm.org
Previous research has used program transformation to introduce parallelism and to exploit
data locality. Unfortunately, these two objectives have usually been considered …
data locality. Unfortunately, these two objectives have usually been considered …
Automated accelerator generation and optimization with composable, parallel and pipeline architecture
CPU-FPGA heterogeneous architectures feature flexible acceleration of many workloads to
advance computational capabilities and energy efficiency in today's datacenters. This …
advance computational capabilities and energy efficiency in today's datacenters. This …
Memory partitioning for multidimensional arrays in high-level synthesis
Memory partitioning is widely adopted to efficiently increase the memory bandwidth by using
multiple memory banks and reducing data access conflict. Previous methods for memory …
multiple memory banks and reducing data access conflict. Previous methods for memory …
Improving high level synthesis optimization opportunity through polyhedral transformations
High level synthesis (HLS) is an important enabling technology for the adoption of hardware
accelerator technologies. It promises the performance and energy efficiency of hardware …
accelerator technologies. It promises the performance and energy efficiency of hardware …