SODA: Stencil with optimized dataflow architecture

Y Chi, J Cong, P Wei, P Zhou - 2018 IEEE/ACM International …, 2018 - ieeexplore.ieee.org
Stencil computation is one of the most important kernels in many application domains such
as image processing, solving partial differential equations, and cellular automata. Many of …

IronMan-Pro: Multiobjective design space exploration in HLS via reinforcement learning and graph neural network-based modeling

N Wu, Y Xie, C Hao - … on Computer-Aided Design of Integrated …, 2022 - ieeexplore.ieee.org
Despite the great success of high-level synthesis (HLS) tools, we observe several
unresolved challenges: 1) the high-level abstraction of HLS programming styles sometimes …

Polyhedral-based data reuse optimization for configurable computing

LN Pouchet, P Zhang, P Sadayappan… - Proceedings of the ACM …, 2013 - dl.acm.org
Many applications, such as medical imaging, generate intensive data traffic between the
FPGA and off-chip memory. Significant improvements in the execution time can be achieved …

IRONMAN GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learning

N Wu, Y Xie, C Hao - Proceedings of the 2021 on Great Lakes …, 2021 - dl.acm.org
Despite the great success of High-Level Synthesis (HLS) tools, we observe several
unresolved challenges: 1) the high-level abstraction of programming styles in HLS conceals …

Optimizing for parallelism and data locality

K Kennedy, KS McKinley - … of the 6th international conference on …, 1992 - dl.acm.org
Previous research has used program transformation to introduce parallelism and to exploit
data locality. Unfortunately, these two objectives have usually been considered …

Automated accelerator generation and optimization with composable, parallel and pipeline architecture

J Cong, P Wei, CH Yu, P Zhang - Proceedings of the 55th Annual Design …, 2018 - dl.acm.org
CPU-FPGA heterogeneous architectures feature flexible acceleration of many workloads to
advance computational capabilities and energy efficiency in today's datacenters. This …

[图书][B] FPGAs for software programmers

D Koch, F Hannig, D Ziener - 2016 - Springer
Dirk Koch · Frank Hannig Daniel Ziener Editors Page 1 Dirk Koch · Frank Hannig Daniel Ziener
Editors FPGAs for Software Programmers Page 2 FPGAs for Software Programmers Page 3 …

Memory partitioning for multidimensional arrays in high-level synthesis

Y Wang, P Li, P Zhang, C Zhang, J Cong - Proceedings of the 50th …, 2013 - dl.acm.org
Memory partitioning is widely adopted to efficiently increase the memory bandwidth by using
multiple memory banks and reducing data access conflict. Previous methods for memory …

Improving high level synthesis optimization opportunity through polyhedral transformations

W Zuo, Y Liang, P Li, K Rupnow, D Chen… - Proceedings of the ACM …, 2013 - dl.acm.org
High level synthesis (HLS) is an important enabling technology for the adoption of hardware
accelerator technologies. It promises the performance and energy efficiency of hardware …

The LEAP FPGA operating system

K Fleming, M Adler - FPGAs for software programmers, 2016 - Springer
FPGAs offer attractive power and performance for many applications, especially relative to
traditional sequential architectures. In spite of these advantages, FPGAs have been …