Fortran High-Level Synthesis: Reducing the barriers to accelerating HPC codes on FPGAs
G Rodriguez-Canal, N Brown, T Dykes… - … Conference on Field …, 2023 - ieeexplore.ieee.org
In recent years the use of FPGAs to accelerate scientific applications has grown, with
numerous applications demonstrating the benefit of FPGAs for high performance workloads …
numerous applications demonstrating the benefit of FPGAs for high performance workloads …
OpenCL FPGA Optimization guided by memory accesses and roofline model analysis applied to tomography acceleration
Backward projection is one of the most time-consuming steps in method-based iterative
reconstruction computed tomography. The 3D back-projection memory access pattern is …
reconstruction computed tomography. The 3D back-projection memory access pattern is …
[HTML][HTML] A cross-platform OpenVX library for FPGA accelerators
FPGAs are an excellent platform to implement computer vision applications, since these
applications tend to offer a high level of parallelism with many data-independent operations …
applications tend to offer a high level of parallelism with many data-independent operations …
X-ray tomography reconstruction accelerated on FPGA through High-Level Synthesis tools
Model-Based Iterative Reconstruction (MBIR) algorithms iteratively use expensive
computational operators of forward and backward projections. The irregular memory access …
computational operators of forward and backward projections. The irregular memory access …
System-level communication performance estimation for DMA-controlled accelerators
The performance of a hardware accelerator is often limited by the communication bandwidth
between local on-chip memories and DRAM across on-chip bus. In this paper, a system …
between local on-chip memories and DRAM across on-chip bus. In this paper, a system …
Memory Aware Design Optimisation for High-Level Synthesis
A Bannwart Perina, J Becker, V Bonato - Journal of Signal Processing …, 2024 - Springer
The FPGA environment is traditionally exotic to high-level software developers, mainly due
to the large difference in the development methodologies. This can be mitigated through …
to the large difference in the development methodologies. This can be mitigated through …
Optimizing performance and energy efficiency in massively parallel systems
R Nozal - 2022 - repositorio.unican.es
Heterogeneous systems are becoming increasingly relevant, due to their performance and
energy efficiency capabilities, being present in all types of computing platforms, from …
energy efficiency capabilities, being present in all types of computing platforms, from …
Avances en la síntesis de alto nivel para la generación de hardware en FPGA: Modelos y programabilidad
Mejorar el rendimiento en sistemas de cómputo ha impulsado el uso de aceleradores como
FPGAs. Este trabajo presenta 2 propuestas que aúnan su programabilidad y rendimiento …
FPGAs. Este trabajo presenta 2 propuestas que aúnan su programabilidad y rendimiento …
[HTML][HTML] Высокоуровневые инструменты трансляции моделей для разработки ПЛИС
ТА Мандрик, МЮ Поленов - … университета. Серия 4 …, 2020 - cyberleninka.ru
Цель работы-сравнение высокоуровневых инструментов, используемых для
разработки современных ПЛИС: HDL coder от компании Mathworks, HLS Compiler от …
разработки современных ПЛИС: HDL coder от компании Mathworks, HLS Compiler от …