40 nm bit-interleaving 12T subthreshold SRAM with data-aware write-assist
YW Chiu, YH Hu, MH Tu, JK Zhao… - … on Circuits and …, 2014 - ieeexplore.ieee.org
This paper presents a new bit-interleaving 12T subthreshold SRAM cell with Data-Aware
Power-Cutoff (DAPC) Write-assist to improve the Write-ability to mitigate increased device …
Power-Cutoff (DAPC) Write-assist to improve the Write-ability to mitigate increased device …
SRAM read and write assist apparatus
C Cheng, CC Chou, JTY Chang - US Patent 8,630,132, 2014 - Google Patents
Abstract A SRAM READ and WRITE assist apparatus comprises a bit line voltage tracking
block, a READ assist timer, a READ assist unit, a WRITE assist unit a WRITE control unit …
block, a READ assist timer, a READ assist unit, a WRITE assist unit a WRITE control unit …
Low power design for future wearable and implantable devices
With the fast progress in miniaturization of sensors and advances in micromachinery
systems, a gate has been opened to the researchers to develop extremely small …
systems, a gate has been opened to the researchers to develop extremely small …
Illumination normalization with time-dependent intrinsic images for video surveillance
Variation in illumination conditions caused by weather, time of day, etc., makes the task
difficult when building video surveillance systems of real world scenes. Especially, cast …
difficult when building video surveillance systems of real world scenes. Especially, cast …
Hi-fi playback: Tolerating position errors in shift operations of racetrack memory
Racetrack memory is an emerging non-volatile memory based on spintronic domain wall
technology. It can achieve ultra-high storage density. Also, its read/write speed is …
technology. It can achieve ultra-high storage density. Also, its read/write speed is …
A 32 nm single-ended single-port 7T static random access memory for low power utilization
In this paper, a seven-transistor static random access memory (SRAM) bit cell with a single
bitline architecture is proposed. This cell is designed at 32 nm and is operational at 300 mV …
bitline architecture is proposed. This cell is designed at 32 nm and is operational at 300 mV …
Half-select free and bit-line sharing 9T SRAM for reliable supply voltage scaling
This paper presents a half-select free 9T SRAM to facilitate reliable SRAM operation in the
near-threshold voltage region. In the proposed SRAM, the half-select disturbance, which …
near-threshold voltage region. In the proposed SRAM, the half-select disturbance, which …
Wide-range many-core SoC design in scaled CMOS: Challenges and opportunities
The system-on-chip (SoC) designs for future Internet of Things (IoT) systems, spanning client
platforms to cloud datacenters, need to deliver uncompromising and scalable performance …
platforms to cloud datacenters, need to deliver uncompromising and scalable performance …
Single-supply 3T gain-cell for low-voltage low-power applications
Logic compatible gain cell (GC)-embedded DRAM (eDRAM) arrays are considered an
alternative to SRAM due to their small size, nonratioed operation, low static leakage, and …
alternative to SRAM due to their small size, nonratioed operation, low static leakage, and …
Memory device and method of controlling leakage current within such a memory device
B Zheng, G Yeung, F ali Bohra - US Patent 9,171,634, 2015 - Google Patents
A memory device includes an array of memory cells arranged as a plurality of rows and
columns, each row being coupled to an associated read word line, and each column forming …
columns, each row being coupled to an associated read word line, and each column forming …