Decimal floating-point: Algorism for computers

MF Cowlishaw - Proceedings 2003 16th IEEE Symposium on …, 2003 - ieeexplore.ieee.org
Decimal arithmetic is the norm in human calculations, and human centric applications must
use a decimal floating point arithmetic to achieve the same results. Initial benchmarks …

Improved design of high-performance parallel decimal multipliers

A Vazquez, E Antelo… - IEEE Transactions on …, 2009 - ieeexplore.ieee.org
The new generation of high-performance decimal floating-point units (DFUs) is demanding
efficient implementations of parallel decimal multipliers. In this paper, we describe the …

Densely packed decimal encoding

M Cowlishaw - IEE Proceedings-Computers and Digital Techniques, 2002 - IET
Chen–Ho encoding is a lossless compression of three binary coded decimal digits into 10
bits using an algorithm which can be applied or reversed using only simple Boolean …

The IBM zEnterprise-196 decimal floating-point accelerator

S Carlough, A Collura, S Mueller… - 2011 IEEE 20th …, 2011 - ieeexplore.ieee.org
Decimal floating-point Arithmetic is widely used in commercial computing applications, such
as financial transactions, where rounding errors prevent the use of binary floating-point …

A radix-10 digit-recurrence division unit: algorithm and architecture

T Lang, A Nannarelli - IEEE Transactions on Computers, 2007 - ieeexplore.ieee.org
In this work, we present a radix-10 division unit that is based on the digit-recurrence
algorithm. The previous decimal division designs do not include recent developments in the …

Customized Floating Point Algorithm for the Ranging System

R Kumar, AAB Raj - 2020 International Conference on System …, 2020 - ieeexplore.ieee.org
This In this work a new algorithm for the system in which space ie size is main concern is
proposed. Using this algorithm we can achieve desired accuracy and preciseness in range …

FPgen-a test generation framework for datapath floating-point verification

M Aharoni, S Asaf, L Fournier… - … high-level design …, 2003 - ieeexplore.ieee.org
FPgen is a new test generation framework targeted toward the verification of the floating
point (FP) datapath, through the generation of test cases. This framework provides the …

Order-preserving encoding formats of floating-point decimal numbers for efficient value comparison

YS Chen, MF Cowlishaw, CJ Crone, F Lee… - US Patent …, 2010 - Google Patents
IF sign bit OFF THEN/* means negative number '! tempbuf= inverse all the bits to make it
positive number lF non-zero bit of tempbufOFF THEN/* must be 0*! resultbuffer= O …

Fast radix-10 multiplication using redundant BCD codes

A Vazquez, E Antelo… - IEEE transactions on …, 2014 - ieeexplore.ieee.org
We present the algorithm and architecture of a BCD parallel multiplier that exploits some
properties of two different redundant BCD codes to speedup its computation: the redundant …

Decimal floating-point multiplication via carry-save addition

MA Erle, MJ Schulte… - 18th IEEE Symposium on …, 2007 - ieeexplore.ieee.org
Decimal multiplication is important in many commercial applications including financial
analysis, banking, tax calculation, currency conversion, insurance, and accounting. This …