Virtual metrology in semiconductor manufacturing: Current status and future prospects

V Maitra, Y Su, J Shi - Expert Systems with Applications, 2024 - Elsevier
Abstract Advanced Process Control (APC) has become an increasingly pressing issue for
the semiconductor industry, particularly in the new era of sub-5nm process technology. To …

Methods of measurement of die temperature of semiconductor elements: A review

K Dziarski, A Hulewicz, P Kuwałek, G Wiczyński - Energies, 2023 - mdpi.com
Monitoring the temperature of a semiconductor component allows for the prediction of
potential failures, optimization of the selected cooling system, and extension of the useful life …

Investigation of nanosheet-FET based logic gates at sub-7 nm technology node for digital IC applications

S Tayal, S Valasa, S Bhattacharya, J Ajayan… - Silicon, 2022 - Springer
The successful fabrication of Nanosheet (NS) FET by Samsung/IBM for below 7 nm
technology nodes has geared up the semiconductor industry towards future electronics. In …

Small Feature‐Size Transistors Based on Low‐Dimensional Materials: From Structure Design to Nanofabrication Techniques

X Fu, Z Liu, H Wang, D Xie, Y Sun - Advanced Science, 2024 - Wiley Online Library
For several decades after Moore's Law is proposed, there is a continuous effort to reduce the
feature‐size of transistors. However, as the size of transistors continues to decrease …

Exploration of underlap induced high-k spacer with gate stack on strain channel cylindrical nanowire FET for enriched performance

R Barik, RS Dhar, MI Hussein - Scientific Reports, 2024 - nature.com
This research explores a comprehensive examination of gate underlap incorporated
strained channel Cylindrical Gate All Around Nanowire FET having enriched performances …

High-mobility transport symmetry and effect of strain on electronic and optical properties in few-layer blue phosphorus

T Wang, B Li - Computational Materials Science, 2023 - Elsevier
As a new type of 2D semiconductor, blue phosphorus (BP) is an ideal material for new
electronic devices, whose performance can be compared with that of black phosphorus. The …

Improved DC Performance of Nanotube Junctionless Field-Effect Transistors with Dielectric Pocket Integration

CK Pandey, DA Kumar, U Nanda - ECS Journal of Solid State …, 2022 - iopscience.iop.org
In this paper, a nanotube architecture of Junctionless FET (JLFET) is investigated wherein it
is observed that the performance characteristics of JLFET are improved by introducing …

Integrating run-to-run control with feedback control for a spatial atomic layer etching reactor

H Wang, M Tom, F Ou, G Orkoulas… - … Research and Design, 2024 - Elsevier
Semiconductor manufacturing employs an intricate framework of processes that require
accurate design specifications at the nanoscale level. Thermal atomic layer etching fulfills …

Linearity performance and harmonic distortion analysis of IGE junctionless silicon nanotube-FET for wireless applications

S Tayal, S Bhattacharya, B Jena, J Ajayan… - Silicon, 2022 - Springer
This manuscript investigates the effect of inner gate engineering (IGE) on the linearity and
harmonic distortion performance of junctionless (JL) silicon-nanotube (Si-NT) FETs for …

A survey on the latest FET technology for samsung industry

AL Rikabi, HTH Salim, GM Ali - AIP Conference Proceedings, 2023 - pubs.aip.org
In semiconductor electronics firms like Samsung, field effect transistor (FET) technology is
the main design layout for high-performance applications. Gate-all-around (GAA) FETs …