FPGA dynamic and partial reconfiguration: A survey of architectures, methods, and applications
Dynamic and partial reconfiguration are key differentiating capabilities of field
programmable gate arrays (FPGAs). While they have been studied extensively in academic …
programmable gate arrays (FPGAs). While they have been studied extensively in academic …
Go ahead: A partial reconfiguration framework
C Beckhoff, D Koch, J Torresen - 2012 IEEE 20th International …, 2012 - ieeexplore.ieee.org
Exploiting the benefits of partial run-time reconfiguration requires efficient tools. In this
paper, we introduce the tool Go Ahead that is able to implement run-time reconfigurable …
paper, we introduce the tool Go Ahead that is able to implement run-time reconfigurable …
RapidSmith: Do-it-yourself CAD tools for Xilinx FPGAs
C Lavin, M Padilla, J Lamprecht… - … Conference on Field …, 2011 - ieeexplore.ieee.org
Creating CAD tools for commercial FPGAs is a difficult task. Closed proprietary device
databases and unsupported interfaces are largely to blame for the lack of CAD research …
databases and unsupported interfaces are largely to blame for the lack of CAD research …
[图书][B] FPGAs: fundamentals, advanced features, and applications in industrial electronics
JJR Andina, E De la Torre Arnanz, MDV Peña - 2017 - taylorfrancis.com
Field Programmable Gate Arrays (FPGAs) are currently recognized as the most suitable
platform for the implementation of complex digital systems targeting an increasing number of …
platform for the implementation of complex digital systems targeting an increasing number of …
Reducing FPGA compile time with separate compilation for FPGA building blocks
Today's FPGA compilation is slow because it compiles and co-optimizes the entire design in
one monolithic mapping flow. This achieves high quality results but also means a long edit …
one monolithic mapping flow. This achieves high quality results but also means a long edit …
Fast and flexible FPGA development using hierarchical partial reconfiguration
To address slow FPGA compilation, researchers have proposed to run separate
compilations for smaller design components in parallel. This approach provides small pages …
compilations for smaller design components in parallel. This approach provides small pages …
Near-memory address translation
Memory and logic integration on the same chip is becoming increasingly cost effective,
creating the opportunity to offload data-intensive functionality to processing units placed …
creating the opportunity to offload data-intensive functionality to processing units placed …
An end-to-end multi-standard OFDM transceiver architecture using FPGA partial reconfiguration
Cognitive radios that are able to operate across multiple standards depending on
environmental conditions and spectral requirements are becoming more important as the …
environmental conditions and spectral requirements are becoming more important as the …
IMPRESS: automated tool for the implementation of highly flexible partial reconfigurable systems with Xilinx Vivado
R Zamacola, AG Martínez, J Mora… - 2018 International …, 2018 - ieeexplore.ieee.org
Dynamic partial reconfiguration is considered a great technique to increase flexibility in
FPGA designs. However, partial reconfiguration flows supported by commercial tools, such …
FPGA designs. However, partial reconfiguration flows supported by commercial tools, such …
Partial reconfiguration on FPGAs in practice—Tools and applications
Run-time reconfiguration of FPGAs has been around in academia for more than two
decades but it is still applied very seldom in industrial applications. This has two main …
decades but it is still applied very seldom in industrial applications. This has two main …