A unified hardware/software runtime environment for FPGA-based reconfigurable computers using BORPH
HKH So, R Brodersen - ACM Transactions on Embedded Computing …, 2008 - dl.acm.org
This paper explores the design and implementation of BORPH, an operating system
designed for FPGA-based reconfigurable computers. Hardware designs execute as normal …
designed for FPGA-based reconfigurable computers. Hardware designs execute as normal …
Proving transaction and system-level properties of untimed SystemC TLM designs
Electronic System Level (ESL) design manages the enormous complexity of todays systems
by using abstract models. In this context Transaction Level Modeling (TLM) is state-of-the-art …
by using abstract models. In this context Transaction Level Modeling (TLM) is state-of-the-art …
[图书][B] System-level validation: high-level modeling and directed test generation techniques
This book covers state-of-the art techniques for high-level modeling and validation of
complex hardware/software systems, including those with multicore architectures. Readers …
complex hardware/software systems, including those with multicore architectures. Readers …
Incorporating efficient assertion checkers into hardware emulation
Assertion-based verification (ABV) is emerging as a paramount technique for industrial-
strength hardware verification, especially through the emerging property specification …
strength hardware verification, especially through the emerging property specification …
[图书][B] Quality-driven SystemC design
D Große, R Drechsler - 2010 - Springer
Faced with the steadily increasing complexity and rapidly shortening timeto-market
requirements designing electronic systems is a very challenging task. To manage this …
requirements designing electronic systems is a very challenging task. To manage this …
A multi-encoding approach for LTL symbolic satisfiability checking
Formal behavioral specifications written early in the system-design process and
communicated across all design phases have been shown to increase the efficiency …
communicated across all design phases have been shown to increase the efficiency …
Improving usability of FPGA-based reconfigurable computers through operating system support
HKH So, RW Brodersen - 2006 International Conference on …, 2006 - ieeexplore.ieee.org
Advances in FPGA-based reconfigurable computers have made them a viable computing
platform for a vast variety of computation demanding areas such as bioinformatics, speech …
platform for a vast variety of computation demanding areas such as bioinformatics, speech …
Automated coverage directed test generation using a cell-based genetic algorithm
Functional verification is a major challenge in the hardware design development cycle.
Defining the appropriate coverage points that capture the design's functionalities is a non …
Defining the appropriate coverage points that capture the design's functionalities is a non …
Automated nonintrusive analysis of electronic system level designs
Due to the ever increasing complexity of hardware systems, designers strive for higher
levels of abstractions in the early stages of the design process. Modeling hardware at the …
levels of abstractions in the early stages of the design process. Modeling hardware at the …
Scalable simulation-based verification of SystemC-based virtual prototypes
M Goli, R Drechsler - 2019 22nd Euromicro Conference on …, 2019 - ieeexplore.ieee.org
Virtual Prototypes (VPs) at the Electronic System Level (ESL) written in SystemC language
using its Transaction Level Modeling (TLM) framework are increasingly adopted by the …
using its Transaction Level Modeling (TLM) framework are increasingly adopted by the …