A survey of architectural techniques for managing process variation

S Mittal - ACM Computing Surveys (CSUR), 2016 - dl.acm.org
Process variation—deviation in parameters from their nominal specifications—threatens to
slow down and even pause technological scaling, and mitigation of it is the way to continue …

Underdesigned and opportunistic computing in presence of hardware variability

P Gupta, Y Agarwal, L Dolecek, N Dutt… - … on Computer-Aided …, 2012 - ieeexplore.ieee.org
Microelectronic circuits exhibit increasing variations in performance, power consumption,
and reliability parameters across the manufactured parts and across use of these parts over …

Speed scaling with an arbitrary power function

N Bansal, HL Chan, K Pruhs - Proceedings of the twentieth annual ACM-SIAM …, 2009 - SIAM
All of the theoretical speed scaling research to date has assumed that the power function,
which expresses the power consumption P as a function of the processor speed s, is of the …

Memory-based PUFs are vulnerable as well: A non-invasive attack against SRAM PUFs

BMSB Talukder, F Ferdaus… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
Memory-based physical unclonable functions (mPUFs) are widely accepted as highly
secure because of the unclonable and immutable nature of manufacturer process variations …

Process variation tolerant 3T1D-based cache architectures

X Liang, R Canal, GY Wei… - 40th Annual IEEE/ACM …, 2007 - ieeexplore.ieee.org
Process variations will greatly impact the stability, leakage power consumption, and
performance of future microprocessors. These variations are especially detrimental to 6T …

Suffering from buffering? Detecting QoE impairments in live video streams

A Ahmed, Z Shafiq, H Bedi… - 2017 IEEE 25th …, 2017 - ieeexplore.ieee.org
Fueled by increasing network bandwidth and decreasing costs, the popularity of over-the-
top large-scale live video streaming has dramatically increased over the last few years. In …

Archipelago: A polymorphic cache design for enabling robust near-threshold operation

A Ansari, S Feng, S Gupta… - 2011 IEEE 17th …, 2011 - ieeexplore.ieee.org
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat
dissipation and power density for modern processors. Dynamic voltage scaling is a widely …

[HTML][HTML] Review of the global trend of interconnect reliability for integrated circuit

Q Lin, H Wu, G Jia - Circuits and Systems, 2018 - scirp.org
Interconnect reliability has been regarded as a discipline that must be seriously taken into
account from the early design phase of integrated circuit (IC). In order to study the status and …

Analysis and optimization of leakage current characteristics in sub-65 nm dual Vt footed domino circuits

N Gong, B Guo, J Lou, J Wang - Microelectronics Journal, 2008 - Elsevier
The inputs and clock signals combination sleep state dependent leakage current
characteristics is analyzed and the optimal sleep state is examined in sub-65nm dual Vt …

[图书][B] Network-on-chip architectures: A holistic design exploration

C Nicopoulos, V Narayanan, CR Das - 2009 - books.google.com
[2]. The Cell Processor from Sony, Toshiba and IBM (STI)[3], and the Sun UltraSPARC T1
(formerly codenamed Niagara)[4] signal the growing popularity of such systems …