Review of the nanoscale FinFET device for the applications in nano-regime

SU Haq, VK Sharma - Current Nanoscience, 2023 - ingentaconnect.com
Background: The insatiable need for low-power and high-performance integrated circuit (IC)
results in the development of alternative options for metal oxide semiconductor field effect …

Recent trends in novel semiconductor devices

A Pandey - Silicon, 2022 - Springer
The VLSI industry has grown a lot for several decades. The Packing density of integrated
circuits has been increased without compromising the functionality. Scaling of …

Optimization of vertically stacked nanosheet FET immune to self-heating

M Balasubbareddy, K Sivasankaran… - Micro and …, 2023 - Elsevier
The self-heating effect (SHE) is one of the major challenges of ultra-scaled devices such as
stacked nanosheet field effect transistor (SNSHFET) for sub 7 nm technology. The DC …

Design and optimization of stress/strain in GAA nanosheet FETs for improved FOMs at sub-7 nm nodes

E Mohapatra, D Jena, S Das, CK Maiti… - Physica Scripta, 2023 - iopscience.iop.org
Stress/strain engineering techniques are employed to boost the performance of Gate-all-
around (GAA) vertically stacked nanosheet field-effect transistors (NSFETs) for 7 nm …

Application of long short-term memory modeling technique to predict process variation effects of stacked gate-all-around Si nanosheet complementary-field effect …

R Butola, Y Li, SR Kola, C Akbar, MH Chuang - Computers and Electrical …, 2023 - Elsevier
Emerging machine-learning (ML) methodology has been overcoming the challenging task of
analyzing the process variation effect of nanoscale devices using 3-D stochastic device …

Machine learning-assisted device modeling with process variations for advanced technology

Y Lyu, W Chen, M Zheng, B Yin, J Li… - IEEE Journal of the …, 2023 - ieeexplore.ieee.org
Process variations (PV), including global variation (GV) and local variation (LV), have
become one of the major issues in advanced technologies, which is crucial for circuit …

Simulation of MoS2 stacked nanosheet field effect transistor

Y Shen, H Tian, T Ren - Journal of Semiconductors, 2022 - iopscience.iop.org
Transition metal dichalcogenides are nowadays appealing to researchers for their excellent
electronic properties. Vertical stacked nanosheet FET (NSFET) based on MoS 2 are …

Machine Learning‐Driven Extraction of Hybrid Compact Models Integrating Neural Networks and Berkeley Short‐Channel Insulated‐Gate Field‐Effect Transistor …

S Eom, S Lee, H Yun, K Cho, S Kim… - Advanced Intelligent …, 2024 - Wiley Online Library
Conventional techniques for extracting physics‐based model parameters are inherently
slow processes and often yield less accurate model parameters because of the inflexibility of …

Comparative analysis of capacitorless DRAM performance according to stacked junctionless gate-all-around structures

J Hwang, I Yun - Solid-State Electronics, 2024 - Elsevier
The characteristic comparison of the capacitor-less DRAMs in the structural form variation is
investigated. Based on the simulation results of the three basic structures, such as circular …

Simulation of different structured gate-all-around FETs for 2 nm node

N Totorica, W Hu, F Li - Engineering Research Express, 2024 - iopscience.iop.org
This paper compares different types of Gate All Around (GAA) FET structures using TCAD
simulation, including Lateral Nanosheet, Lateral Nanowire, Vertical Nanosheet, and Vertical …