[图书][B] On-chip communication architectures: system on chip interconnect

S Pasricha, N Dutt - 2010 - books.google.com
Over the past decade, system-on-chip (SoC) designs have evolved to address the ever
increasing complexity of applications, fueled by the era of digital convergence …

Exploring serial vertical interconnects for 3D ICs

S Pasricha - Proceedings of the 46th Annual Design Automation …, 2009 - dl.acm.org
Three-dimensional integrated circuits (3D ICs) offer a promising solution to overcome the on-
chip communication bottleneck and improve performance over traditional two-dimensional …

System and method for designing integrated circuits that employ adaptive voltage scaling optimization

A Tetelbaum - US Patent 8,539,424, 2013 - Google Patents
BACKGROUND Circuit designers use electronic design automation (EDA) tools, a category
of computer aided design (CAD) tools, to design and lay out electronic circuits, including …

ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip

S Pasricha, N Dutt - 2008 Asia and South Pacific Design …, 2008 - ieeexplore.ieee.org
As application complexity continues to increase, multiprocessor systems-on-chip (MPSoC)
with tens to hundreds of processing cores are becoming the norm. While computational …

A multi-granularity power modeling methodology for embedded processors

YH Park, S Pasricha, FJ Kurdahi… - IEEE Transactions on …, 2010 - ieeexplore.ieee.org
With power becoming a major constraint for multiprocessor embedded systems, it is
becoming important for designers to characterize and model processor power dissipation. It …

Black box ESL power estimation for loosely-timed TLM models

G Onnebrink, R Leupers, G Ascheid… - 2016 International …, 2016 - ieeexplore.ieee.org
Design space exploration (DSE) at system level needs to cover all parameters and has to
find the best trade-off between performance and power of modern heterogeneous multi-and …

[图书][B] Power estimation on electronic system level using linear power models

S Schuermans, R Leupers - 2019 - Springer
This book is based on my dissertation. Thus, it presents my work in the area of power
estimation at Electronic System Level as a research assistant of Professor Leupers at the …

PowerDepot: Integrating IP-based power modeling with ESL power analysis for multi-core SoC designs

CW Hsu, JL Liao, SC Fang, CC Weng… - Proceedings of the 48th …, 2011 - dl.acm.org
In this paper, we introduce an integrated power methodology for multi-core SoC designs. It
features not only a bottom-up IP-based power modeling for all kinds of IP components …

Evaluating carbon nanotube global interconnects for chip multiprocessor applications

S Pasricha, FJ Kurdahi, N Dutt - IEEE transactions on very large …, 2009 - ieeexplore.ieee.org
In ultra-deep submicrometer (UDSM) technologies, the current paradigm of using copper
(Cu) interconnects for on-chip global communication is rapidly becoming a serious …

Designing fault-tolerant component based applications with a model driven approach

B Hamid, A Radermacher, A Lanusse… - … for Embedded and …, 2008 - Springer
The requirement for higher reliability and availability of systems is continuously increasing
even in domains not traditionally strongly involved in such issues. Solutions are expected to …