AI/ML algorithms and applications in VLSI design and technology

D Amuru, A Zahra, HV Vudumula, PK Cherupally… - Integration, 2023 - Elsevier
An evident challenge ahead for the integrated circuit (IC) industry is the investigation and
development of methods to reduce the design complexity ensuing from growing process …

Chip design with machine learning: a survey from algorithm perspective

W He, X Li, X Song, Y Hao, R Zhang, Z Du… - Science China …, 2023 - Springer
Chip design with machine learning (ML) has been widely explored to achieve better
designs, lower runtime costs, and no human-in-the-loop process. However, with tons of …

Fast logic optimization using decision trees

BA De Abreu, A Berndt, IS Campos… - … on Circuits and …, 2021 - ieeexplore.ieee.org
This work evaluates the use of Decision Trees (DTs) methods for a fast logic minimization of
Boolean functions. The proposed DT approach is compared to traditional Espresso logic …

DeepSeq: Deep Sequential Circuit Learning

S Khan, Z Shi, M Li, Q Xu - 2024 Design, Automation & Test in …, 2024 - ieeexplore.ieee.org
In this work, we propose DeepSeq, a novel representation learning framework for sequential
netlists. It employs a graph neural network (GNN) with customized propagation to capture …

A Circuit Domain Generalization Framework for Efficient Logic Synthesis in Chip Design

Z Wang, L Chen, J Wang, X Li, Y Bai, X Li… - arXiv preprint arXiv …, 2023 - arxiv.org
Logic Synthesis (LS) plays a vital role in chip design--a cornerstone of the semiconductor
industry. A key task in LS is to transform circuits--modeled by directed acyclic graphs (DAGs) …

Machine-learning-driven architectural selection of adders and multipliers in logic synthesis

J Cheng, Y Xiao, Y Shao, G Dong, S Lyu… - ACM Transactions on …, 2023 - dl.acm.org
Designing high-performance adders and multiplier components for diverse specifications
and constraints is of practical concern. However, selecting the best architecture for adder or …

[HTML][HTML] Accuracy recovery: A decomposition procedure for the synthesis of partially-specified boolean functions

A Costamagna, G De Micheli - Integration, 2023 - Elsevier
Abstract Logic Synthesis From Partial Specifications (LSFPS) is the problem of finding the
hardware implementation of a Boolean function from a partial knowledge of its care set. The …

Logic synthesis for generalization and learning addition

Y Miyasaka, X Zhang, M Yu, Q Yi… - … Design, Automation & …, 2021 - ieeexplore.ieee.org
Logic synthesis generates a logic circuit of a given Boolean function, where the size and
depth of the circuit are optimized for small area and low delay. On the other hand, machine …

Pushing the limits of machine design: Automated CPU design with AI

S Cheng, P Jin, Q Guo, Z Du, R Zhang, Y Tian… - arXiv preprint arXiv …, 2023 - arxiv.org
Design activity--constructing an artifact description satisfying given goals and constraints--
distinguishes humanity from other animals and traditional machines, and endowing …

DAG-aware Synthesis Orchestration

Y Li, M Liu, M Ren, A Mishchenko… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
Modern logic synthesis techniques use multi-level technology-independent representations
like And-Inverter-Graphs (AIGs) for digital logic. This involves structural rewriting …