Recent advances in very-large-scale integration (VLSI) technologies have offered the
capability of integrating thousands of processing elements onto a single silicon microchip …

Continuing advances in semiconductor technology, coupled with an increasing concern for
energy efficiency, have led to an industry-wide shift in focus towards modular designs that …

Conventional oblivious routing algorithms are either not application-aware or assume that
each flow has its own private channel to ensure deadlock avoidance. We present a …

Virtual channels (VC) and multiple physical (MP) networks are two alternative methods to
provide better performance, support quality-of-service, and avoid protocol deadlocks in …

We present DARSIM, a parallel, highly configurable, cycle-level network-on-chip simulator
based on an ingress-queued wormhole router architecture. The parallel simulation engine …

We present hornet, a parallel, highly configurable, cycle-level multicore simulator based on
an ingress-queued wormhole router network-on-chip (NoC) architecture. The parallel …

We present HORNET, a parallel, highly configurable, cycle-level multicore simulator based
on an ingress-queued worm-hole router NoC architecture. The parallel simulation engine …

Recent years have seen the increased adoption of Coarse-Grained Reconfigurable
Architectures (CGRAs) as flexible, energy-efficient compute accelerators. Obtaining …

The present invention relates to a method for limiting the throughput of a communication in a
meshed network, com prising the following steps: allocating fixed paths to commu nications …

Novel low-diameter network topologies such as Slim Fly (SF) offer significant cost and power
advantages over the established Fat Tree, Clos, or Dragonfly. To spearhead the adoption of …